Abstract: Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip.

Abstract: Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip.

Abstract: Various semiconductor chip devices and methods of assembling the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a frame to a surface of a substrate. The surface of the substrate is adapted to hold a first semiconductor chip that includes an upper surface. The frame includes an internal wall that is adapted to engage plural sidewalls of the first semiconductor chip. A portion of the internal wall and at least a portion of the upper surface are adapted to define an internal space.

Abstract: A method of fabricating laminate assemblies determines the ideal weight (W) of underfill to be dispensed, based on the size of the semiconductor die and the gap between the die and the laminate substrate. Underfill is dispensed in a single step in an amount between 1.1W and 1.3W to form fillets that cover at least 15% of the height of the semiconductor die on all four sides of the die. The amount of underfill ensures that the fillet coverage imbalance is 30% or less for each of the pairs of opposing sides of the die, thereby improving solder joint reliability.

Abstract: A method of fabricating laminate assemblies determines the ideal weight (W) of underfill to be dispensed, based on the size of the semiconductor die and the gap between the die and the laminate substrate. Underfill is dispensed in a single step in an amount between 1.1W and 1.3W to form fillets that cover at least 15% of the height of the semiconductor die on all four sides of the die. The amount of underfill ensures that the fillet coverage imbalance is 30% or less for each of the pairs of opposing sides of the die, thereby improving solder joint reliability.

Abstract: A heat spreader-package assembly is provided having a heat spreader mounted to a package board with an adhesive. The heat spreader has an upper portion and a plurality of sidewalls extending from the upper portion. The heat spreader has a flange that extends from the sidewalls continuously about a periphery of the upper portion and has a plurality of holes. The holes allow the uncured adhesive to flow therethrough. When the adhesive has cured, a head is formed from the adhesive on an upper side of the flange to establish a riveted connection.

Abstract: An extruded heat exchanger that reduces manufacturing costs and material waste, without compromising heat spreading effects. The heat exchanger has an upper surface that is thermally coupled to a heat sink. Two sidewalls extend only from opposite edges of the upper surface. A flange extends from each of the opposing sidewalls.

Abstract: A method for performing inspection of raised electrical contacts, such as BGA and flip-chip-type contacts, and associated underlying vias. An electrical or electronic device or component having a major surface is provided including an array of closely spaced apart BGA flip-chip-type raised contacts with respective underlying vias. An area-of-interest (AOI), including at least one BGA or flip-chip-type contact/via structure is selected. The row containing the AOI is isolated, by computed tomography imaging, via electrical testing, or by removal, for example, from the electrical or electronic device or component. The AOI is mounted on an X-ray transparent substrate; and X-ray transmission imaging of the AOI is performed to inspect the at least one BGA or flip-chip-type contact/via structure for the presence of misalignments, voids, and delaminations.