Abstract: Bond sites on an integrated circuit chip are connected to bond sites on a package by photolithographically defining and selectively plating an air bridge between the chip and spaced-apart metallized bond regions of the package. A layer of dry photoresist is laminated onto top surfaces of each of the chip and the support package, so that photoresist bridges an air gap between the chip and the package. Next, the masking material is patterned, to expose the bond sites on the chip and the package. Over the entirety of the patterned structure, a thin plating-seed barrier metal layer is non-selectively formed. The seed metal layer is then covered with a second mask layer which is photolithographically patterned to expose a portion of the barrier seed metal layer extending between bond sites of the chip and the package. A second relatively thick metal layer is electroplated on the exposed seed metal layer, to form a conductive bridge between the chip and the package.