Abstract: An associative processing memory system for concurrent data searching and concurrent data processing which includes content addressable memory (CAM) array having multiple CAM words; a multiplexer for executing one of the input devices and for passing an output of one of the input devices; an interface register logic block for storing instructions in a command register and control and status information in a control and status register; a match circuit for executing a match instruction for performing a masked comparison of data in every CAM word in the CAM array to a search pattern; a read circuit for executing a read instruction for reading one CAM word in the CAM array wherein the CAM word is selected using a response register A and a multiple response resolver (MRR); a write circuit for executing a write instruction for performing a masked write operation to every CAM word indicated by a bit set in a select vector; a shift circuit for executing a shift instruction for shifting the response register A up or