Abstract: Methods and apparatus for auctioning securities. The methods and apparatus receive one or more backstop bids for the securities from one or more backstop bidders and implement a real-time auction of securities over the Internet. The methods and apparatus determine a clearing price for the auction, the clearing price being determined such that all of the securities are distributed and allocate at least a portion of the securities to the one or more backstop bidders if the clearing price is less than the backstop bids.

Abstract: A light weight, state-of-the-art, easy to use, short- and/or long-handled gardening implement providing at least raking and hoeing capabilities on a single tool head, so that there is no need to change tool heads or to add and/or delete parts. The rake part of the rake part of the tool head has an optional number of operative tines of optional length and width designed to till soil to appreciable depth. The operative hoe part of the tool head may be positioned on either or both ends of the tool head. The handle is positioned relative to the tool head and balanced according to the weight distribution of the tool parts on the tool head providing for maximum effectiveness. The hoe blade is shaped and sized for easy and rapid insertion into the soil providing for easy extraction of deeply rooted weeds without unnecessarily disrupting adjacent soil or damaging nearby plants.

Abstract: A plurality of curved plates which are adapted to be mounted on an embossing roll are identically engraved with an embossing pattern that matches the plate dimensions, permitting them to be interchanged or replaced without disrupting pattern discontinuity. In one embodiment, the pattern is created to match a given plate by laying out a skew grid matching plate corners, and using grid parallelograms as pattern unit cells. In another embodiment, an existing doubly periodic pattern is minimally distorted to match the plate geometry. In still another embodiment an embossing pattern is modified to fit an embossing roll having a given circumference.

Abstract: A decubitus mat includes a plurality of individual cells (16) which are pressurized by air from an air supply (10) through air supply lines (12) and metering orifices (14). A polymer sensor/vent structure (20) is mounted on a top surface of each cell to be contacted by a body (22) resting on the mat. The sensor/vent structure defines a plurality of polymer-filled channels (28) and a vent valve (26) which is biased to a closed position. As the body heats the polymer, it undergoes a phase change and expands causing biasing forces (30) which bias the vent valve to open. When the vent valve opens, the air in the cell is released, providing an air flow to remove pooled moisture under the body. The vented cell collapses, transferring support to adjoining cells until it no longer contacts the body. Once removed from the body, the air flow in the cell cools the polymer, closing the vent, allowing the cell to re-pressurize.

Abstract: A plurality of curved plates which are adapted to be mounted on an embossing roll are identically engraved with an embossing pattern that matches the plate dimensions, permitting them to be interchanged or replaced without disrupting pattern discontinuity. In one embodiment, the pattern is created to match a given plate by laying out a skew grid matching plate corners, and using grid parallelograms as pattern unit cells. In another embodiment, an existing doubly periodic pattern is minimally distorted to match the plate geometry.

Abstract: Techniques for achieving the effects of significantly reducing the amount of computer memory needed to simulate the behavior of a multi-stage pipelined processor, as well as, significantly increasing the performance of the simulation process by eliminating the storing and copying of redundant information are described. These beneficial effects are achieved by reordering the chronological sequence of execution of software models of the various pipeline stages with respect to the actual instruction-flow sequence implemented by the processor hardware. This approach takes advantage of the independence of the stages within a cycle to make the results computed by a previous stage directly available to its subsequent stage without the use of transient data space or data copying. In particular, it is shown how to apply this technique to the simulation of a multi-parallel-stage VLIW array processor, such as the manifold array (ManArray) processor.

Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized testcases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data, stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

Abstract: An electron beam source includes a cathode having an electron emission surface including an active area for emission of electrons and a cathode shield assembly including a conductive shield disposed in proximity to the electron emission surface of the cathode. The shield has an opening aligned with the active area. The electron beam source further includes a device for stimulating emission of electrons from the active area of the cathode, electron optics for forming the electrons into an electron beam and a vacuum enclosure for maintaining the cathode at high vacuum. The cathode may be a negative electron affinity photocathode formed on a light-transmissive substrate. The shield protects non-emitting areas of the emission surface from contamination and inhibits cathode materials from contaminating components of the electron beam source. The cathode may be moved relative to the opening in the shield so as to align an new active area with the opening.

Abstract: Noise reducing circuits for electronic receiving instruments, such as telephone receivers in headsets or handsets that are used in noisy locations, provide compensation of the set's receiver unit-to-error microphone transfer function to enhance the noise reduction. Further circuits provide pre-conditioning of the incoming voice signal to make the noise cancellation more effective. The tendency of these noise cancelling circuits to oscillate is substantially lessened by added circuitry which rapidly detects onset of oscillation and momentarily reduces the noise cancellation without interrupting the incoming speech path altogether.