Abstract: A method and apparatus for minimizing processor idle time resulting from the transfer of data between the processor and a resource. An intelligent First In First Out (FIFO) queuing scheme provides a basis for the transfer of data between a host bus and a system bus or between a bus and a resource. The FIFO posts write requests and provides an acknowledgement back to an originating resource on the host bus that the write request has been received. This acknowledgement enables the processor to continue processing. The FIFO further provides for detection of conditions where posted information may be processed out of First In First Out order and conditions where FIFO registers may be read from or data fields overwritten. This capability additionally minimizes idle time by reducing the number of posted items that need to be written to a resource during a read cycle to that resource.