Patents by Inventor Edward Sprague

Edward Sprague has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240068974
    Abstract: A method for identifying damage in a component of a wind turbine includes placing a conductive element onto at least one surface of the component of the wind turbine. The method also includes electrically connecting the conductive element into an electrical circuit. Further, the method includes monitoring a status of the electrical circuit to identify the damage in the component. In particular, when the status of the electrical circuit is open, damage is likely present in the component, and when the status of the electrical circuit is closed, damage is unlikely present in the component. Moreover, the method includes transmitting the status of the electrical circuit to a user interface for display.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Daniel Edward Jordy, Bhaveshkumar Mahendrakumar Kachhia, Aaron Lee Sprague, Dhanushkodi Durai Mariappan, William Max Gobeli
  • Patent number: 10656200
    Abstract: A high volume system level testing of devices with POP structures such as POP memories includes a POP array that includes floating nests that can adjust in the XY direction in order to align individually with respective pads found on the DUTs. The floating nests also include a mechanically fixed PCB that is fixed to the nest and can either mate to a memory contactor array that can accept an unattached POP device such as a memory or can include an attached memory in order to accommodate different POP requirements. In a method, the POP array includes a number of floating nests with memory loaded are aligned and presented to their respective DUTs just prior to testing the combined DUT and POP memory assemblies.
    Type: Grant
    Filed: July 16, 2017
    Date of Patent: May 19, 2020
    Assignee: ADVANTEST TEST SOLUTIONS, INC.
    Inventors: Gregory Cruzan, Gilberto Oseguera, Karthik Ranganathan, Edward Sprague
  • Publication number: 20180024188
    Abstract: A high volume system level testing of devices with POP structures such as POP memories includes a POP array that includes floating nests that can adjust in the XY direction in order to align individually with respective pads found on the DUTs. The floating nests also include a mechanically fixed PCB that is fixed to the nest and can either mate to a memory contactor array that can accept an unattached POP device such as a memory or can include an attached memory in order to accommodate different POP requirements. In a method, the POP array includes a number of floating nests with memory loaded are aligned and presented to their respective DUTs just prior to testing the combined DUT and POP memory assemblies.
    Type: Application
    Filed: July 16, 2017
    Publication date: January 25, 2018
    Inventors: GREGORY CRUZAN, GILBERTO OSEGUERA, KARTHIK RANGANATHAN, EDWARD SPRAGUE
  • Patent number: 8565610
    Abstract: Embodiments of the invention are described in which correlated virtual data streams are managed within an optical network connection. In certain embodiments of the invention, a client signal is allocated across a plurality of transport wavelength channels according to various transposition methods. The assignment of portions of the client signal to corresponding wavelengths may depend on various factors including channel utilization within the transport network and skew characteristics between particular wavelengths.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: October 22, 2013
    Assignee: Infinera Corporation
    Inventors: Edward Sprague, Charles H. Joyner
  • Patent number: 7672301
    Abstract: A distribution stage is disclosed comprising a plurality of inputs coupled to a plurality of first stage switching devices, a plurality of outputs coupled to a plurality of second stage switching devices, and a distribution configuration. The distribution configuration is configured to receive a plurality of bandwidth units (BU's) from each first stage switching device, and to distribute at least one BU from each first stage switching device to each second stage switching device, such that each second stage switching device is assured of receiving at least one BU from each first stage switching device. In effect, the distribution stage ensures that each first stage switching device has a logical link to each second stage switching device. In one embodiment, the distribution stage is configured in accordance with a distribution configuration that is static.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: March 2, 2010
    Assignee: Ciena Corporation
    Inventors: Daniel E. Klausmeier, Edward Sprague
  • Publication number: 20090034976
    Abstract: Embodiments of the invention are described in which correlated virtual data streams are managed within an optical network connection. In certain embodiments of the invention, a client signal is allocated across a plurality of transport wavelength channels according to various transposition methods. The assignment of portions of the client signal to corresponding wavelengths may depend on various factors including channel utilization within the transport network and skew characteristics between particular wavelengths.
    Type: Application
    Filed: June 18, 2008
    Publication date: February 5, 2009
    Inventors: Edward Sprague, Charles Joyner
  • Publication number: 20080044183
    Abstract: An optical transmission network is inherently asynchronous due to the utilization of a variable overhead ratio (V-OHR). The network architecture makes extensive use of OEO regeneration, i.e., deals with any electronic reconditioning to correct for transmission impairments, such as, for example, FEC encoding, decoding and re-encoding, signal reshaping, retiming as well as signal regeneration. The optical transmission network includes a plesiochronous clocking system with intermediate nodes designed to operate asynchronously with a single local frequency clock without complicated network synchronization schemes employing high cost clocking devices such as phase locked loop (PLL) control with crystal oscillators and other expensive system components.
    Type: Application
    Filed: October 22, 2007
    Publication date: February 21, 2008
    Applicant: INFINERA CORPORATION
    Inventors: Drew Perkins, Ting-Kuang Chiang, Edward Sprague, Daniel Murphy
  • Publication number: 20080037984
    Abstract: An optical transmission network is inherently asynchronous due to the utilization of a variable overhead ratio (V-OHR). The network architecture makes extensive use of OEO regeneration, i.e., deals with any electronic reconditioning to correct for transmission impairments, such as, for example, FEC encoding, decoding and re-encoding, signal reshaping, retiming as well as signal regeneration. The optical transmission network includes a plesiochronous clocking system with intermediate nodes designed to operate asynchronously with a single local frequency clock without complicated network synchronization schemes employing high cost clocking devices such as phase locked loop (PLL) control with crystal oscillators and other expensive system components.
    Type: Application
    Filed: October 22, 2007
    Publication date: February 14, 2008
    Applicant: Infinera Corporation
    Inventors: Drew Perkins, Ting-Kuang Chiang, Edward Sprague, Daniel Murphy
  • Publication number: 20070211742
    Abstract: A line card in a network node having a local memory coupled to a local controller and local logic circuit. The local memory in the line card stores state information for signals processed by the line card itself, as well as state information for signals processed by other line cards. The logic circuit and controller implement a same fault detection and signal processing algorithms as all other line cards in the group, to essentially effectuate a distributed and local hardware based control of automatic protection switching (APS) without interrupting a central processor. The line card also performs error checking and supervisory functions to ensure consistency of state among the line cards.
    Type: Application
    Filed: January 30, 2007
    Publication date: September 13, 2007
    Applicant: INFINERA CORPORATION
    Inventors: Tjandra Trisno, Edward Sprague, Scott Young
  • Publication number: 20070009262
    Abstract: The present invention provides a system, apparatus and method for modularly adapting a network node architecture to function in one of a plurality of potential node types. The architecture includes a configurable switching element, integrated optics, and a plurality of modules that allow a “type” of node to be adapted and configured within the base architecture. The module interfaces may be optical or electrical and be used to construct various different types of nodes including regenerators, add/drop nodes, terminal nodes, and multi-way nodes using the same base architecture.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 11, 2007
    Inventors: Drew Perkins, Ting-Kuang Chiang, Marco Sosa, Mark Yin, Edward Sprague
  • Publication number: 20070002430
    Abstract: A system, apparatus and method are described for controlling the gain across one or more amplifier nodes within an optical span. In one embodiment, a fast local amplifier constant gain control loop is provided that maintains a constant gain across an amplifier node for each of the channels within an optical signal. A slow link level gain setting control loop is provided to set and/or adjust the target gain on the amplifier node(s). A gain adjust sequence is performed by the slow link level gain setting control loop to adjust the target gain(s) in response to various events and mechanisms. A “time of flight” protection method is also provided to ensure consistency between the fast local amplifier gain control loop and the slow link level gain setting control loop.
    Type: Application
    Filed: June 22, 2006
    Publication date: January 4, 2007
    Applicant: INFINERA CORPORATION
    Inventors: Matthew Mitchell, Robert Taylor, Edward Sprague
  • Publication number: 20050286521
    Abstract: Client signals to be transported in a transmission network, particularly an optical transmission network, may have different payload envelope rates and are digitally mapped on the client egress side into first transport frames (also referred to as iDTF frames, or intra-node or internal digital transport frames), at the client side for intra-transport within terminal network elements (NEs) and further digitally mapped into second transport frames (also referred to as DTFs or digital transport frames) for inter-transport across the network or a link which, through byte stuffing carried out in the first transport frames so that they always have the same frame size. As a result, the system of framers provides for a DTF format to always have a uniformly universal frame rate throughout the network supporting any client signal frequency, whether a standard client payload or a proprietary client payload, as long as its rate is below payload envelope rate of the client signal.
    Type: Application
    Filed: June 16, 2005
    Publication date: December 29, 2005
    Applicant: Infinera Corporation
    Inventors: Ting-Kuang Chiang, Drew Perkins, Edward Sprague, Daniel Murphy
  • Publication number: 20050157713
    Abstract: A distribution stage is disclosed comprising a plurality of inputs coupled to a plurality of first stage switching devices, a plurality of outputs coupled to a plurality of second stage switching devices, and a distribution configuration. The distribution configuration is configured to receive a plurality of bandwidth units (BU's) from each first stage switching device, and to distribute at least one BU from each first stage switching device to each second stage switching device, such that each second stage switching device is assured of receiving at least one BU from each first stage switching device. In effect, the distribution stage ensures that each first stage switching device has a logical link to each second stage switching device. In one embodiment, the distribution stage is configured in accordance with a distribution configuration that is static.
    Type: Application
    Filed: May 2, 2003
    Publication date: July 21, 2005
    Inventors: Daniel Klausmeier, Edward Sprague