Abstract: Errors occurring on a hardware bus of a hypervisor-based system may be handled in software monitors in the hypervisor-based system. When an error occurs, guest partitions on the hypervisor-based system may be notified of the error through a monitor executing in each guest partition. Only guest partitions affected by the error may be shut down or provided other instructions for taking an action in response to the error.

Abstract: Errors occurring on a hardware bus of a hypervisor-based system may be handled in software monitors in the hypervisor-based system. When an error occurs, guest partitions on the hypervisor-based system may be notified of the error through a monitor executing in each guest partition. Only guest partitions affected by the error may be shut down or provided other instructions for taking an action in response to the error.

Abstract: An apparatus and system having both PCI Root Port (RP) device and Direct Memory Access (DMA) End Point device functionality is disclosed. The apparatus is for use in an input/output (I/O) system interconnect module (IOSIM) device. A DMA/RP module includes a RP portion and one or more DMA/RP portions. The RP portion has one or more queue pipes and is configured to function as a standard PCIe Root Port device. Each of the DMA/RP portions includes DMA engines and DMA input and output channels, and is configured to behave more like an End Point device. The DMA/RP module also includes one or more PCIe hard core portions, an ICAM (I/O Caching Agent Module), and at least one PCIe service block (PSB). *The hard core portion couples the DMA/RP module and IOSIM device to an I/O device via a PCIe link, and the ICAM transitions data to a host memory device operating system.

Abstract: Methods and apparatus for allocating access to a buffer of a host device to buffer data transferred between a controller of the host device and one or more remote devices are disclosed. The host device is configured to couple to each of the one or more remote devices through one or more corresponding dedicated lanes. Buffer access is allocated by determining, for each of one or more remote devices coupled to the host device, a number of dedicated lanes between the host device and each of the one or more remote devices and allocating access to the buffer of the host device for each of the one or more remote devices responsive to the determined number of dedicated lanes.

Abstract: Variable compensation for part to part skew of components in a substrate-mounted circuit is described. The variability may be provided through a computer software program acting on a programmable delay buffer such that compensation for a skewed signal may be continuously checked against a reference signal or through other methods. The skewed signal may be delayed until the signal matches, within a predetermined margin of error, the reference.

Abstract: Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a serial data transfer medium. A data buffer receives and stores user defined data from the parallel storage medium. A control data facility that is distinct from the data buffer forms and transmits control data from the sender of the frame to the recipient of the frame via a path that does not include the data buffer. The control data facility includes respectively different dedicated logic for asynchronously generating each of the following: special character sequences, frame delimiters, headers, and cyclic redundancy checksums. A switching facility receives the user defined data from the data buffer. The switching facility also receives control data from the control data facility.

Abstract: An Input/Output (I/O) subsystem is provided for transferring frames containing frame control data from a serial data transfer medium to a parallel storage medium. The subsystem includes independent components for processing different portions of the received character stream. The subsystem includes a sequence recognition mechanism for receiving and identifying any of a plurality of digital data bit sequences. The sequences represent channel status information from the data transfer medium. The sequence recognition mechanism provides an interrupt signal derived from the sequences. A frame recognition mechanism responds to the interrupt signal. The frame recognition mechanism receives and identifies a start-of-frame delimiter or an end-of-frame delimiter from the data transfer medium. The frame recognition mechanism provides a frame status signal. A frame receiving mechanism responds to the frame status signal. The frame receiving mechanism receives and identifies a frame header from the data transfer medium.

Abstract: Apparatus is provided for use in an Input/Output (I/O) subsystem. The I/O subsystem is coupled to a serial data transfer medium that transmits data from a sender to a recipient. The I/O subsystem processes a frame comprising user defined data and frame control data. The frame is received over the serial data transfer medium. The apparatus includes a mechanism for receiving and validating the frame from the serial data transfer medium. The receiving mechanism transmits the user defined data to a first-in, first-out (FIFO) buffer. A mechanism is provided for forming a block header. The block header comprises control data that are used by the recipient of the user defined data. The block header forming mechanism is distinct from the FIFO buffer. A switching mechanism is coupled to receive the block header and a subset of the user defined data. The recipient has a parallel storage medium.