Patents by Inventor Edward T. Malley
Edward T. Malley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11303456Abstract: A single architected instruction to produce a signature for a message is obtained. The instruction is executed, and the executing includes determining a sign function of a plurality of sign functions supported by the instruction to be performed. Input for the instruction is obtained, and the input includes a message and a cryptographic key. A signature is produced based on the sign function to be performed and the input. The signature is to be used to verify the message.Type: GrantFiled: February 15, 2019Date of Patent: April 12, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
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Patent number: 11175923Abstract: A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.Type: GrantFiled: February 13, 2017Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, James J. Bonanno, Adam B. Collura, Bruce C. Giamei, Christian Jacobi, Jang-Soo Lee, Edward T. Malley, Lawrence J. Powell, Jr., Anthony Saporito
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Patent number: 11157240Abstract: A single architected instruction to perform scalar multiplication for cryptographic operations is obtained. The instruction is executed, and the executing includes determining a scalar multiply function of a plurality of scalar multiply functions supported by the instruction to be performed. Input for the scalar multiply function is obtained, and the input includes at least one source component and a scalar value. The scalar multiply function is performed using the input to provide an output to be used in a cryptographic operation.Type: GrantFiled: February 15, 2019Date of Patent: October 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
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Patent number: 11108567Abstract: A single architected instruction to verify a signed message is executed. The executing includes determining a verify function of a plurality of verify functions supported by the instruction to be performed and obtaining input for the instruction. The input includes a message and a key. Based on the verify function to be performed and the input, a signature of the message is verified.Type: GrantFiled: February 15, 2019Date of Patent: August 31, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
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Patent number: 11075763Abstract: A single architected instruction to produce a signature for a message is executed. The executing includes determining an encrypted sign function of a plurality of encrypted sign functions supported by the instruction to be performed and obtaining input for the instruction. The input includes a message and an encrypted cryptographic key. Based on the encrypted sign function to be performed and the input, a signature to be used to verify the message is produced.Type: GrantFiled: February 15, 2019Date of Patent: July 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
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Publication number: 20200267000Abstract: A single architected instruction to verify a signed message is executed. The executing includes determining a verify function of a plurality of verify functions supported by the instruction to be performed and obtaining input for the instruction. The input includes a message and a key. Based on the verify function to be performed and the input, a signature of the message is verified.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
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Publication number: 20200266999Abstract: A single architected instruction to produce a signature for a message is executed. The executing includes determining an encrypted sign function of a plurality of encrypted sign functions supported by the instruction to be performed and obtaining input for the instruction. The input includes a message and an encrypted cryptographic key. Based on the encrypted sign function to be performed and the input, a signature to be used to verify the message is produced.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
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Publication number: 20200267001Abstract: A single architected instruction to produce a signature for a message is obtained. The instruction is executed, and the executing includes determining a sign function of a plurality of sign functions supported by the instruction to be performed. Input for the instruction is obtained, and the input includes a message and a cryptographic key. A signature is produced based on the sign function to be performed and the input. The signature is to be used to verify the message.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
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Publication number: 20200264843Abstract: A single architected instruction to perform scalar multiplication for cryptographic operations is obtained. The instruction is executed, and the executing includes determining a scalar multiply function of a plurality of scalar multiply functions supported by the instruction to be performed. Input for the scalar multiply function is obtained, and the input includes at least one source component and a scalar value. The scalar multiply function is performed using the input to provide an output to be used in a cryptographic operation.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
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Patent number: 10599431Abstract: Embodiments of the present invention provide a system for balancing a global completion table (GCT) in a microprocessor via frontend steering or stalls. A non-limiting example of the system includes an instruction dispatch unit (IDU) that includes an instruction queue and the system includes an instruction sequencing unit (ISU) that includes a GCT having a first area and a second area. The IDU is configured to determine whether a full group of instructions exist in the instruction queue and to determine whether additional instructions will be received by the instruction queue in a subsequent cycle. The IDU is configured to stall the instruction queue for at least one cycle until a full group of instructions is accumulated at the instruction queue upon determining that additional instructions will be received by the instruction queue in subsequent cycle.Type: GrantFiled: July 17, 2017Date of Patent: March 24, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, David S. Hutton, Christian Jacobi, Edward T. Malley, Anthony Saporito
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Patent number: 10540183Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.Type: GrantFiled: October 31, 2017Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, David S. Hutton, Edward T. Malley, Brian R. Prasky, John G. Rell, Jr.
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Patent number: 10365928Abstract: Embodiments of the invention are directed to methods for handling scratch registers in a processor. The method includes receiving a cracked instruction in an instruction dispatch unit of the processor. The method further includes decoding the cracked instruction into a group of micro-operations. Based on a determination that the instruction group uses a scratch register, determining if the scratch register is used in other groups of micro-operations. Based on a determination that the scratch register is not used in other instruction groups, allocating a physical register for use as the scratch register without creating a mapper entry for the scratch register.Type: GrantFiled: November 1, 2017Date of Patent: July 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, David S. Hutton, Christian Jacobi, Edward T. Malley, Anthony Saporito
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Publication number: 20190129717Abstract: Embodiments of the invention are directed to methods for handling scratch registers in a processor. The method includes receiving a cracked instruction in an instruction dispatch unit of the processor. The method further includes decoding the cracked instruction into a group of micro-operations. Based on a determination that the instruction group uses a scratch register, determining if the scratch register is used in other groups of micro-operations. Based on a determination that the scratch register is not used in other instruction groups, allocating a physical register for use as the scratch register without creating a mapper entry for the scratch register.Type: ApplicationFiled: November 1, 2017Publication date: May 2, 2019Inventors: Gregory W. Alexander, David S. Hutton, Christian Jacobi, Edward T. Malley, Anthony Saporito
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Publication number: 20190018676Abstract: Embodiments of the present invention provide a system for balancing a global completion table (GCT) in a microprocessor via frontend steering or stalls. A non-limiting example of the system includes an instruction dispatch unit (IDU) that includes an instruction queue and the system includes an instruction sequencing unit (ISU) that includes a GCT having a first area and a second area. The IDU is configured to determine whether a full group of instructions exist in the instruction queue and to determine whether additional instructions will be received by the instruction queue in a subsequent cycle. The IDU is configured to stall the instruction queue for at least one cycle until a full group of instructions is accumulated at the instruction queue upon determining that additional instructions will be received by the instruction queue in subsequent cycle.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: Gregory W. Alexander, David S. Hutton, Christian Jacobi, Edward T. Malley, Anthony Saporito
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Publication number: 20180232234Abstract: A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.Type: ApplicationFiled: February 13, 2017Publication date: August 16, 2018Inventors: GREGORY W. ALEXANDER, JAMES J. BONANNO, ADAM B. COLLURA, BRUCE C. GIAMEI, CHRISTIAN JACOBI, JANG-SOO LEE, EDWARD T. MALLEY, LAWRENCE J. POWELL, Jr., ANTHONY SAPORITO
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Patent number: 9971601Abstract: Dynamic resource allocation is provided in which additional resources, such as additional architected registers, are provided to an instruction, if it is determined that resources in addition to those configured to be provided to the instruction are to be used for the particular instruction. An instruction to be executed is dispatched on a pipe of a pipeline and that pipe is configured to have a set number of architected registers for use by the instruction. However, if one or more other architected registers are needed, those additional architected registers are dynamically allocated to the instruction by assigning one or more source ports of an additional pipe to the instruction.Type: GrantFiled: February 13, 2015Date of Patent: May 15, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, Brian D. Barrick, Fadi Y. Busaba, Wen H. Li, Edward T. Malley
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Publication number: 20180067745Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, David S. Hutton, Edward T. Malley, Brian R. Prasky, John G. Rell, JR.
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Patent number: 9875107Abstract: As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.Type: GrantFiled: January 19, 2015Date of Patent: January 23, 2018Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, David S. Hutton, Edward T. Malley, Brian R. Prasky, John G. Rell, Jr.
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Patent number: 9766896Abstract: Embodiments include optimizing the grouping of instructions in a microprocessor. Aspects include receiving a first clump of instructions from a streaming buffer, pre-decoding each of instructions for select information and sending the instructions to an instruction queue. Aspects further include storing initial grouping information for the instructions in a local register, wherein the initial grouping information is based on the select information. Aspects further include updating the initial group information stored in the local register when additional pre-decode information becomes available and grouping the instructions that are ready to be dispatched into a dispatch group based on the grouping information stored in the local register. Aspects further include dispatching the dispatch group to an issue unit.Type: GrantFiled: September 1, 2015Date of Patent: September 19, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fadi Y. Busaba, Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Jr., Eric M. Schwarz, Aaron Tsai
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Patent number: 9710278Abstract: Embodiments include optimizing the grouping of instructions in a microprocessor. Aspects include receiving a first clump of instructions from a streaming buffer, pre-decoding each of instructions for select information and sending the instructions to an instruction queue. Aspects further include storing initial grouping information for the instructions in a local register, wherein the initial grouping information is based on the select information. Aspects further include updating the initial group information stored in the local register when additional pre-decode information becomes available and grouping the instructions that are ready to be dispatched into a dispatch group based on the grouping information stored in the local register. Aspects further include dispatching the dispatch group to an issue unit.Type: GrantFiled: September 30, 2014Date of Patent: July 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fadi Y. Busaba, Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Jr., Eric M. Schwarz, Aaron Tsai