Abstract: Methods, systems, and apparatus for EM communications. One of the methods includes determining, at a first device, that a second device is present; initiating a half duplex communication with the second device; configuring communication with the second device including determining whether full duplex communication is available; in response to a determination that full duplex communication is not available, communicating with the second device in half duplex mode; and in response to a determination that full duplex communication is available, communication with the second device in full duplex mode.

Abstract: A system, such as a server rack, includes rack mountable devices that communicate using one or more extremely high frequency (EHF) communication devices. A rack mountable device includes a rack mountable chassis including multiple sides, and a circuit board along a side of the rack mountable chassis, the circuit board having a surface. The EHF communication devices are positioned along the side of the rack mountable chassis and attached to the surface of the circuit board. Each of the EHF communication devices is configured to convert between an EHF electromagnetic signal and an electrical data signal. The EHF communication devices form EHF communication channels with other EHF communication devices in other rack mountable devices, or in the server rack to provide high bandwidth data transfer utilizing space on the sides of the rack mountable device.

Abstract: A system, such as a server rack, includes rack mountable devices that communicate using one or more extremely high frequency (EHF) communication devices. A rack mountable device includes a rack mountable chassis including multiple sides, and a circuit board along a side of the rack mountable chassis, the circuit board having a surface. The EHF communication devices are positioned along the side of the rack mountable chassis and attached to the surface of the circuit board. Each of the EHF communication devices is configured to convert between an EHF electromagnetic signal and an electrical data signal. The EHF communication devices form EHF communication channels with other EHF communication devices in other rack mountable devices, or in the server rack to provide high bandwidth data transfer utilizing space on the sides of the rack mountable device.

Abstract: Methods, systems, and apparatus for EM communications. One of the methods includes determining, at a first device, that a second device is present; initiating a half duplex communication with the second device; configuring communication with the second device including determining whether full duplex communication is available; in response to a determination that full duplex communication is not available, communicating with the second device in half duplex mode; and in response to a determination that full duplex communication is available, communication with the second device in full duplex mode.

Abstract: A system, such as a server rack, includes rack mountable devices that communicate using one or more extremely high frequency (EHF) communication devices. A rack mountable device includes a rack mountable chassis including multiple sides, and a circuit board along a side of the rack mountable chassis, the circuit board having a surface. The EHF communication devices are positioned along the side of the rack mountable chassis and attached to the surface of the circuit board. Each of the EHF communication devices is configured to convert between an EHF electromagnetic signal and an electrical data signal. The EHF communication devices form EHF communication channels with other EHF communication devices in other rack mountable devices, or in the server rack to provide high bandwidth data transfer utilizing space on the sides of the rack mountable device.

Abstract: Methods, systems, and apparatus for EM communications. One of the methods includes determining, at a first device, that a second device is present; initiating a half duplex communication with the second device; configuring communication with the second device including determining whether full duplex communication is available; in response to a determination that full duplex communication is not available, communicating with the second device in half duplex mode; and in response to a determination that full duplex communication is available, communication with the second device in full duplex mode.

Abstract: Methods, systems, and apparatus for EM communications. One of the methods includes determining, at a first device, that a second device is present; initiating a half duplex communication with the second device; configuring communication with the second device including determining whether full duplex communication is available; in response to a determination that full duplex communication is not available, communicating with the second device in half duplex mode; and in response to a determination that full duplex communication is available, communication with the second device in full duplex mode.

Abstract: The invention provides a cache architecture that selectively powered-up a portion of data array in a pipelined cache architecture. A tag array is first powered-up, but the data array is not powered-up during this time, to determine whether there is a tag hit from the decoded index address comparing to the tag compare data. If there is a tag hit, during a later time, a data array is then powered-up at that time to enable a cache line which corresponds with the tag hit for placing onto a data bus. The power consumed by the tag represents a fraction of the power consumed by the data array. A significant power is conserved during the time in which the tag array is assessing whether a tag hit occurs while the data array is not powered-on at this point.

Abstract: The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of the adders by cutting the latch delay while not requiring complex clocking.

Abstract: The invention provides a system and method for executing a replacement selection algorithm embedded in each associativity of a cache memory architecture. Each associativity in a cache has an internal control logic that governs the process for replacing a cache line when a certain condition occurs, such as a presence of a TagHit. A designated set of control signals is used in an associativity control logic for corresponding with an external control logic. An associativity control logic within an associativity provides an internal capability to determine whether a TagHit condition occurs as well as volunteering the associativity for replacement. The preferred replacement algorithm is implemented using an approximation to Not the Most Recently Used Associativity (NMRU).

Abstract: Occurrence of uncorrectable errors in a stored sector of data which includes a data block, an error checking and correcting (ECC) block and an error detecting (CRC) block is detected. ECC logic is connected to a data bus and responsive to the ECC block in the sector, for generating an error polynomial identifying a location and a value for correctable errors in the sector. CRC logic is connected to the data bus and responsive to the CRC block in the sector for generating a syndrome identifying detected errors in the data block. An evaluation logic circuit is included that is coupled to the ECC logic and the CRC logic and responsive to the error polynomial and the syndrome for generating an uncorrectable error signal if the detected errors do not match the correctable errors. The error checking and correcting code is a Reed-Solomon code as in the X3B11 standard. Likewise the CRC code is a Reed-Solomon code as in the X3B11 standard.

Abstract: Occurrence of uncorrectable errors in a stored sector of data which includes a data block, an error checking and correcting (ECC) block and an error detecting (CRC) block is detected. ECC logic is connected to a data bus and responsive to the ECC block in the sector, for generating an error polynomial identifying a location and a value for correctable errors in the sector. CRC logic is connected to the data bus and responsive to the CRC block in the sector for generating a syndrome identifying detected errors in the data block. An evaluation logic circuit is included that is coupled to the ECC logic and the CRC logic and responsive to the error polynomial and the syndrome for generating an uncorrectable error signal if the detected errors do not match the correctable errors. The error checking and correcting code is a Reed-Solomon code as in the X3B11 standard. Likewise the CRC code is a Reed-Solomon code as in the X3B11 standard.

Abstract: An improved high speed two phase clock counter is disclosed. The counter includes a plurality of counter cells coupled to a transition pattern recognizer. Through the use of these elements a counter is provided that overcomes the power consumption and size limitation problems associated with known high speed counters.