Patents by Inventor Edward Teoh

Edward Teoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9053923
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Azat Latypov, Edward Teoh Kah Ching, He Yi
  • Publication number: 20150126034
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Azat Latypov, Edward Teoh Kah Ching, He Yi
  • Patent number: 8611584
    Abstract: A system and method for performing optical navigation selectively uses portions of captured frame of image data for cross-correlation for displacement estimation, which can reduce the power consumption and/or increase the tracking performance at higher speed usage.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: December 17, 2013
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Edward Teoh, Willie Song
  • Patent number: 8453089
    Abstract: An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: May 28, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Kah Ching Edward Teoh, Vito Dai
  • Patent number: 8453087
    Abstract: An approach is provided for preemptive design verification via partial pattern matching. Data corresponding to one or more problematic layout patterns associated with an integrated circuit manufacturing process is received. Data corresponding to a block of intellectual property including a layout design is received. At least a boundary of the layout design is scanned against the one or more problematic layout patterns. One or more partial matches of the one or more problematic layout patterns are identified at least at the boundary. Results are generated indicating the one or more partial matches.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Kah Ching Edward Teoh
  • Publication number: 20130086542
    Abstract: An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Inventors: Kah Ching Edward Teoh, Vito Dai
  • Publication number: 20130031521
    Abstract: An approach is provided for preemptive design verification via partial pattern matching. Data corresponding to one or more problematic layout patterns associated with an integrated circuit manufacturing process is received. Data corresponding to a block of intellectual property including a layout design is received. At least a boundary of the layout design is scanned against the one or more problematic layout patterns. One or more partial matches of the one or more problematic layout patterns are identified at least at the boundary. Results are generated indicating the one or more partial matches.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Kah Ching Edward Teoh
  • Publication number: 20110038508
    Abstract: A system and method for performing optical navigation selectively uses portions of captured frame of image data for cross-correlation for displacement estimation, which can reduce the power consumption and/or increase the tracking performance at higher speed usage.
    Type: Application
    Filed: August 17, 2009
    Publication date: February 17, 2011
    Applicant: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
    Inventors: Edward Teoh, Willie Song