Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: In-line data packet transformations. A transformation engine obtains data to be transformed and determines a transformation to be applied to the data. The determining uses an input/output control block that includes at least one field to be used in determining the transformation to be applied. Based on determining the transformation to be applied, the transformation is performed.

Abstract: In-line data packet transformations. A transformation engine obtains data to be transformed and determines a transformation to be applied to the data. The determining uses an input/output control block that includes at least one field to be used in determining the transformation to be applied. Based on determining the transformation to be applied, the transformation is performed.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, wherein a cached data item is assigned to a first core of the processor cores for exclusively executing an atomic primitive by the first core. The method comprises, while the execution of the atomic primitive is not completed by the first core, receiving from a second core at a cache controller a request for accessing the data item. In response to determining that a second request of the data item is received from a third core, of the plurality of processor cores, before receiving the request of the second core, a rejection message may be returned to the second core.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Abstract: Embodiments relate to controlling a temperature of a solid state memory device using queue depth management by monitoring an operating temperature of each of a plurality of solid state drives of the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds local device threshold values, the method includes receiving an indication that one or more local measures have been taken by the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds a secondary global threshold value, the method includes reducing a queue length for the solid state memory device.

Abstract: Embodiments relate to controlling a temperature of a solid state memory device using queue depth management by monitoring an operating temperature of each of a plurality of solid state drives of the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds local device threshold values, the method includes receiving an indication that one or more local measures have been taken by the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds a secondary global threshold value, the method includes reducing a queue length for the solid state memory device.

Abstract: Embodiments relate to controlling a temperature of a solid state memory device using queue depth management by monitoring an operating temperature of each of a plurality of solid state drives of the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds local device threshold values, the method includes receiving an indication that one or more local measures have been taken by the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds a secondary global threshold value, the method includes reducing a queue length for the solid state memory device.

Abstract: Embodiments relate to controlling a temperature of a solid state memory device using queue depth management by monitoring an operating temperature of each of a plurality of solid state drives of the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds local device threshold values, the method includes receiving an indication that one or more local measures have been taken by the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds a secondary global threshold value, the method includes reducing a queue length for the solid state memory device.

Abstract: Embodiments relate to lifecycle management of solid state memory adaptors. Aspects of the invention include monitoring a remaining life of each of a plurality of solid state memory adaptors in a system and creating a log of a wearing of each of the plurality of solid state memory adaptors. Aspects further include transmitting the log to a service element and receiving a supplemental data from the service element and determining a threshold value for each of the plurality of solid state memory adaptors. Based on determining that the remaining life of one of the plurality of solid state memory adaptors is below the threshold value for the one of the plurality of solid state memory adaptors, aspects also include creating a service call to request that the one of the solid state memory adaptors be replaced.

Abstract: Embodiments relate to controlling a temperature of a solid state memory device using queue depth management by monitoring an operating temperature of each of a plurality of solid state drives of the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds local device threshold values, the method includes receiving an indication that one or more local measures have been taken by the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds a secondary global threshold value, the method includes reducing a queue length for the solid state memory device.

Abstract: Embodiments relate to lifecycle management of solid state memory adaptors. Aspects of the invention include monitoring a remaining life of each of a plurality of solid state memory adaptors in a system and creating a log of a wearing of each of the plurality of solid state memory adaptors. Aspects further include transmitting the log to a service element and receiving a supplemental data from the service element and determining a threshold value for each of the plurality of solid state memory adaptors. Based on determining that the remaining life of one of the plurality of solid state memory adaptors is below the threshold value for the one of the plurality of solid state memory adaptors, aspects also include creating a service call to request that the one of the solid state memory adaptors be replaced.

Abstract: Embodiments relate to controlling a temperature of a solid state memory device using queue depth management by monitoring an operating temperature of each of a plurality of solid state drives of the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds local device threshold values, the method includes receiving an indication that one or more local measures have been taken by the solid state memory device. Based on a determination that the operating temperature of one of the plurality of solid state drives exceeds a secondary global threshold value, the method includes reducing a queue length for the solid state memory device.

Abstract: Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result.