Patents by Inventor Edward W. Jaeck

Edward W. Jaeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7563645
    Abstract: An electronic package of the kind having a folded substrate is provided. The substrate is configured so that a stress concentration is created where folding is desired. In the present example, the stress concentration is created with first a resilient metal ground layer that resists bending and has an edge that promotes the creation of a stress concentration in a flexible layer at or near the edge. A second metal ground layer resists bending in another portion of the substrate, and also has an edge creating a stress concentration in a different area of the flexible layer. The portions of the substrate having the first and second resilient metal ground layers can be folded over one another with substantially no bending in these portions, while a fold portion between the edges bends to allow for folding of the substrate.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: July 21, 2009
    Assignee: Intel Corporation
    Inventor: Edward W. Jaeck
  • Patent number: 7057116
    Abstract: An apparatus including a substrate having dimensions suitable as a support circuit for at least one integrated circuit, the substrate comprising a laterally extending plication region defining first and second longitudinal portions; a plurality of conductive traces distributed in a first distribution plane of the substrate and extending transversely through the plication region; a first and second layers of conductive material in a second distribution plane of the first portion and second portion, respectively, of the substrate; at least one conductive bridge extending transversely through less than the entire plication region in the second distribution plane and coupled to the first continuous layer and to the second continuous layer; and at least one externally accessible contact point coupled to at least one of the first and second layers. A method of forming a support circuit and a system including a package.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Geoffery L. Reid, Edward W. Jaeck
  • Patent number: 6992376
    Abstract: An electronic package of the kind having a folded substrate is provided. The substrate is configured so that a stress concentration is created where folding is desired. In the present example, the stress concentration is created with first a resilient metal ground layer that resists bending and has an edge that promotes the creation of a stress concentration in a flexible layer at or near the edge. A second metal ground layer resists bending in another portion of the substrate, and also has an edge creating a stress concentration in a different area of the flexible layer. The portions of the substrate having the first and second resilient metal ground layers can be folded over one another with substantially no bending in these portions, while a fold portion between the edges bends to allow for folding of the substrate.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventor: Edward W. Jaeck
  • Patent number: 6841855
    Abstract: An electronic package is provided, having a flexible substrate, a first plurality of conductors, and a second plurality of conductors. The flexible substrate has first and second portions with a fold portion between the first and second portions, and is folded at the fold portion to position the second portion over the first portion. Each one of the first plurality of conductors runs from the first portion over the fold portion onto the second portion. Each one of the second plurality of conductors runs from the first portion onto the second portion without running over the fold portion.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: January 11, 2005
    Assignee: Intel Corporation
    Inventors: Edward W. Jaeck, Chia-Pin Chiu
  • Publication number: 20040238206
    Abstract: An apparatus including a substrate having dimensions suitable as a support circuit for at least one integrated circuit, the substrate comprising a laterally extending plication region defining first and second longitudinal portions; a plurality of conductive traces distributed in a first distribution plane of the substrate and extending transversely through the plication region; a first and second layers of conductive material in a second distribution plane of the first portion and second portion, respectively, of the substrate; at least one conductive bridge extending transversely through less than the entire plication region in the second distribution plane and coupled to the first continuous layer and to the second continuous layer; and at least one externally accessible contact point coupled to at least one of the first and second layers. A method of forming a support circuit and a system including a package.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 2, 2004
    Inventors: Geoffery L. Reid, Edward W. Jaeck
  • Publication number: 20040212063
    Abstract: An electronic package is provided, having a flexible substrate, a first plurality of conductors, and a second plurality of conductors. The flexible substrate has first and second portions with a fold portion between the first and second portions, and is folded at the fold portion to position the second portion over the first portion. Each one of the first plurality of conductors runs from the first portion over the fold portion onto the second portion. Each one of the second plurality of conductors runs from the first portion onto the second portion without running over the fold portion.
    Type: Application
    Filed: April 28, 2003
    Publication date: October 28, 2004
    Inventors: Edward W. Jaeck, Chia-Pin Chiu