Patents by Inventor Edward Wai Yeung Liu
Edward Wai Yeung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088845Abstract: A high voltage driver is provided that includes a PMOS stack of transistors arranged in series between a power supply node and an output node. The high voltage driver also includes an NMOS stack of transistors arranged between the output node and ground.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Inventor: Edward Wai Yeung LIU
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Publication number: 20230074461Abstract: Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Inventors: Edward Wai Yeung LIU, Vladimir APARIN
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Patent number: 11502706Abstract: Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.Type: GrantFiled: October 2, 2020Date of Patent: November 15, 2022Assignee: QUALCOMM IncorporatedInventors: Edward Wai Yeung Liu, Vladimir Aparin
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Publication number: 20220109460Abstract: Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Inventors: Edward Wai Yeung LIU, Vladimir APARIN
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Publication number: 20190334513Abstract: A successive approximation register analog-to-digital converter (SAR ADC) includes a comparator with low input referred noise that uses a small capacitor array for improved communication speed. The comparator includes a cross-coupled pair of transistors, a first input transistor, a second input transistor, a first negative capacitance device and a second negative capacitance device. The first and second transistors are in a differential configuration. A gate of the first input transistor is coupled to a first array of capacitors and a gate of the second input transistor is coupled to a second array of capacitors. The first negative capacitance device is coupled between the gate of the first input transistor and a first polarity node. The second negative capacitance device is coupled between the gate of the second input transistor and a second polarity node.Type: ApplicationFiled: April 25, 2018Publication date: October 31, 2019Inventor: Edward Wai Yeung Liu
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Patent number: 10187078Abstract: A data converter includes multiple subunits to convert an input such as a radio frequency (RF) signal. The subunits are selected to sample the input in an order that varies over time. Two or more subunits are enabled at the same time. The selected subunits are configured to convert the input from an analog signal to a digital signal or vice versa.Type: GrantFiled: July 14, 2017Date of Patent: January 22, 2019Assignee: QUALCOMM IncorporatedInventor: Edward Wai Yeung Liu
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Publication number: 20180226983Abstract: A data converter includes multiple subunits to convert an input such as a radio frequency (RF) signal. The subunits are selected to sample the input in an order that varies over time. Two or more subunits are enabled at the same time. The selected subunits are configured to convert the input from an analog signal to a digital signal or vice versa.Type: ApplicationFiled: July 14, 2017Publication date: August 9, 2018Inventor: Edward Wai Yeung LIU
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Patent number: 8428194Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: GrantFiled: February 17, 2012Date of Patent: April 23, 2013Assignee: NVIDIA CorporationInventors: Timothy C. Kuo, Mansour Keramat, Edward Wai Yeung Liu
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Publication number: 20120149322Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: ApplicationFiled: February 17, 2012Publication date: June 14, 2012Applicant: NVIDIA CORPORATIONInventors: Timothy C. Kuo, Mansour Keramat, Edward Wai Yeung Liu
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Patent number: 8121221Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: GrantFiled: July 15, 2008Date of Patent: February 21, 2012Assignee: Nvidia CorporationInventors: Timothy C. Kuo, Mansour Keramat, Edward Wai Yeung Liu
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Patent number: 7606546Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: April 18, 2008Date of Patent: October 20, 2009Assignee: Nvidia CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Patent number: 7558348Abstract: A radio frequency antenna system and high-speed digital data link are disclosed to, among other things, reduce electromagnetic interference (“EMI”) at relatively high data rates while reducing the manufacturing complexities associated with conventional data links. In one embodiment, a radio frequency (“RF”) antenna system includes an antenna and an RF radio coupled to the antenna for receiving wireless RF signals. In particular, the RF radio is configured to digitize RF signals at a fixed data rate to form digitized data signals and to apply the digitized data signals at a variable data rate to a high-speed digital link. The variable data rate distributes the signal energy of the digitized data signals over one or more bands of frequencies, thereby beneficially altering an EMI spectral profile describing emissions that develop as the digitized data signals are transported through a channel.Type: GrantFiled: May 18, 2005Date of Patent: July 7, 2009Assignee: Nvidia CorporationInventors: Tao Liu, Mansour Keramat, Mehrdad Heshami, Feng Bao, Timothy C. Kuo, Douglas J. Hogberg, Bo Liang, Edward Wai Yeung Liu
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Patent number: 7548740Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: December 12, 2007Date of Patent: June 16, 2009Assignee: Nvidia CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Patent number: 7542749Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: December 12, 2007Date of Patent: June 2, 2009Assignee: NVIDIA CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Patent number: 7499690Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: December 12, 2007Date of Patent: March 3, 2009Assignee: NVIDIA CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Publication number: 20080273637Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: ApplicationFiled: July 15, 2008Publication date: November 6, 2008Applicant: NVIDIA CORPORATIONInventors: Timothy C. Kuo, Mansour Keramat, Edward Wai Yeung Liu
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Patent number: 7447490Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: GrantFiled: May 18, 2005Date of Patent: November 4, 2008Assignee: Nvidia CorporationInventors: Timothy C. Kuo, Mansour Keramat, Edward Wai Yeung Liu
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Patent number: 7397776Abstract: A method for autonomously and dynamically optimizing transmission power of an endpoint in a wireless network includes the step of monitoring a received signal strength, a received signal quality and a transmission error rate of a signal transmitted between an access point in the wireless network and the endpoint at a given transmission power and transmission speed. The method also includes the steps of reducing the transmission power when the received signal strength, the received signal quality and the transmission error rate are at respectively acceptable operating levels and then monitoring the transmission error rate of the signal transmitted at the reduced transmission power level. The method further includes the step of adjusting one of the transmission power or the transmission speed based on whether the transmission error rate of the signal transmitted at the reduced transmission power is still at its respective acceptable operating level.Type: GrantFiled: September 28, 2004Date of Patent: July 8, 2008Assignee: NVIDIA CorporationInventors: Thomas Maufer, Suresh Rajan, Edward Wai Yeung Liu, Sameer Nanda, Paul J. Sidenblad
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Patent number: 7389095Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: May 18, 2005Date of Patent: June 17, 2008Assignee: Nvidia CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Patent number: 5032744Abstract: A regenerative latch includes a fully differential amplifier with two inputs and two outputs and two positive feedback paths, each path coupling each of the two outputs to one of the two inputs through a capacitor. Hence, during the reset phase, the two capacitors will block all DC voltages thereby enabling offset cancellation of the amplifier. During the regeneration phase, the two positive feedback paths drive the amplifier quickly into saturation. The output of the regenerative latch may be used to drive a second stage latch to reduce metastability and to reduce the gain requirements for the latch. The transistor channels of the input transistors of the second stage latch are reverse biased into depletion regions to reduce the input capacitance of the second latch during reset. Such low input capacitance speeds up the regeneration of the first stage latch.Type: GrantFiled: October 31, 1989Date of Patent: July 16, 1991Assignee: VLSI Technology, Inc.Inventor: Edward Wai Yeung Liu