Abstract: According to an example, a device for processing data is suggested, said device comprising a first component, wherein the first software component is arranged for receiving the data; a security processor for receiving said data and a first signature, wherein the security processor is arranged for determining based on the first signature whether the data are valid; for determining a second signature for the data; and for conveying the second signature to the first component.

Abstract: An embodiment relates to a method for processing data that includes (a) calculating a second identifier based on input data, (b) conducting a first operation comparing the second identifier with a first identifier, and (c) conducting a second operation comparing the second identifier with a modified first identifier.

Abstract: A cyclic redundancy check (CRC) can be determined with fewer resources within a communication system. A CRC interface component is configured to receive an array of bits as an input via an N-bit data pathway, and receive a CRC previous output from a feedback component coupled to a CRC output, in which N can comprise an integer greater than one. A parallel CRC component can be configured to generate a CRC current output from a plurality of parallel processing pipelines that are configured to concurrently process at least a part of the array of bits and the CRC previous output with a set of parallel CRC logic operations. The set of CRC logic operations can include a masking operation and a parity operation.

Abstract: An embodiment relates to a method for processing data that includes (a) calculating a second identifier based on input data, (b) conducting a first operation comparing the second identifier with a first identifier, and (c) conducting a second operation comparing the second identifier with a modified first identifier.

Abstract: According to an example, a device for processing data is suggested, said device comprising a first component, wherein the first software component is arranged for receiving the data; a security processor for receiving said data and a first signature, wherein the security processor is arranged for determining based on the first signature whether the data are valid; for determining a second signature for the data; and for conveying the second signature to the first component.

Abstract: A cyclic redundancy check (CRC) can be determined with fewer resources within a communication system. A CRC interface component is configured to receive an array of bits as an input via an N-bit data pathway, and receive a CRC previous output from a feedback component coupled to a CRC output, in which N can comprise an integer greater than one. A parallel CRC component can be configured to generate a CRC current output from a plurality of parallel processing pipelines that are configured to concurrently process at least a part of the array of bits and the CRC previous output with a set of parallel CRC logic operations. The set of CRC logic operations can include a masking operation and a parity operation.

Abstract: One embodiment of the present invention relates to a low-power micro-controller unit having both a standby micro-controller optimized for low power consumption and a main micro-controller optimized for high performance. A power supply is coupled to the main micro-controller and the standby micro-controller. The power supply provides power to one or more of the low-power, standby micro-controller and the high performance, main micro-controller by separate power supply paths, depending on system needs. The separate power supply paths allow the main micro-controller and the standby micro-controller operate independent of each other. During a low-power standby operating mode, power can be disconnected to the main micro-controller, while providing power to the standby micro-controller, thereby eliminating the leakage current associated with the large number of transistors in the main micro-controller, while still retaining the computational capabilities of the standby micro-controller.

Abstract: One embodiment of the present invention relates to a low-power micro-controller unit having both a standby micro-controller optimized for low power consumption and a main micro-controller optimized for high performance. A power supply is coupled to the main micro-controller and the standby micro-controller. The power supply provides power to one or more of the low-power, standby micro-controller and the high performance, main micro-controller by separate power supply paths, depending on system needs. The separate power supply paths allow the main micro-controller and the standby micro-controller operate independent of each other. During a low-power standby operating mode, power can be disconnected to the main micro-controller, while providing power to the standby micro-controller, thereby eliminating the leakage current associated with the large number of transistors in the main micro-controller, while still retaining the computational capabilities of the standby micro-controller.