Patents by Inventor Edward William Kiewra

Edward William Kiewra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10014377
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward William Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9704958
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward William Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20170179238
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: CHENG-WEI CHENG, EDWARD WILLIAM KIEWRA, AMLAN MAJUMDAR, DEVENDRA K. SADANA, KUEN-TING SHIU, YANNING SUN
  • Publication number: 20170179237
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 22, 2017
    Inventors: CHENG-WEI CHENG, EDWARD WILLIAM KIEWRA, AMLAN MAJUMDAR, DEVENDRA K. SADANA, KUEN-TING SHIU, YANNING SUN
  • Patent number: 8610172
    Abstract: Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Edward William Kiewra, Kuen-Ting Shiu
  • Publication number: 20130153964
    Abstract: Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Edward William Kiewra, Kuen-Ting Shiu
  • Patent number: 7119545
    Abstract: A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: October 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ishtiaq Ahsan, Ronald Gene Filippi, Roy Charles Iggulden, Edward William Kiewra, Ping-Chuan Wang
  • Patent number: 6444565
    Abstract: A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Christopher Adam Feild, Roy Charles Iggulden, Rajiv Vasant Joshi, Edward William Kiewra
  • Patent number: 6433436
    Abstract: A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: Christopher Adam Feild, Roy Charles Iggulden, Rajiv Vasant Joshi, Edward William Kiewra
  • Patent number: 5670018
    Abstract: A back end of the line dry etch method is disclosed. Etching of a mask oxide and temporary (sacrificial) silicon mandrel occurs following the formation of gate stacks and tungsten studs. The mask oxide is etched selectively to tungsten and silicon through the use of a polymerizing oxide etch. The silicon is etched selectively to both silicon nitride, silicon oxide, and tungsten. The process removes the silicon mandrel and associated silicon residual stringers by removing backside helium cooling, while using HBr as the single species etchant, and by adjusting the duration, the pressure, and the electrode gaps during the silicon etch process. The silicon may be undoped polysilicon, doped polysilicon, or single crystal silicon.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: September 23, 1997
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: Elke Eckstein, Birgit Hoffman, deceased, Edward William Kiewra, Waldemar Walter Kocon, Marc Jay Weiss