Patents by Inventor Edwin A. Arevalo

Edwin A. Arevalo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379376
    Abstract: Disclosed herein are approaches for reducing EUV dose during formation of a patterned metal oxide photoresist. In one approach, a method may include providing a stack of layers atop a substrate, the stack of layers comprising a film layer, and implanting the film layer with ions. The method may further include depositing a metal oxide photoresist atop the film layer, and patterning the metal oxide photoresist.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Rajesh Prasad, Yung-Chen Lin, Zhiyu Huang, Fenglin Wang, Chi-I Lang, Hoyung David Hwang, Edwin A. Arevalo, KyuHa Shim
  • Patent number: 8450193
    Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise a platen to hold a wafer in a single-wafer process chamber during ion implantation, the platen including: a wafer clamping mechanism to secure the wafer onto the platen and to provide a predetermined thermal contact between the wafer and the platen, and one or more heating elements to pre-heat and maintain the platen in a predetermined temperature range above room temperature. The apparatus may also comprise a post-cooling station to cool down the wafer after ion implantation. The apparatus may further comprise a wafer handling assembly to load the wafer onto the pre-heated platen and to remove the wafer from the platen to the post-cooling station.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: May 28, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan Gerald England, Richard Stephen Muka, Edwin A. Arevalo, Ziwei Fang, Vikram Singh
  • Patent number: 7642150
    Abstract: Techniques for forming shallow junctions are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for forming shallow junctions. The method may comprise generating an ion beam comprising molecular ions based on one or more materials selected from a group consisting of: digermane (Ge2H6), germanium nitride (Ge3N4), germanium-fluorine compounds (GFn, wherein n=1, 2, or 3), and other germanium-containing compounds. The method may also comprise causing the ion beam to impact a semiconductor wafer.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: January 5, 2010
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Edwin A. Arevalo, Christopher R. Hatem, Anthony Renau, Jonathan Gerald England
  • Publication number: 20080108208
    Abstract: Techniques for forming shallow junctions are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for forming shallow junctions. The method may comprise generating an ion beam comprising molecular ions based on one or more materials selected from a group consisting of: digermane (Ge2H6), germanium nitride (Ge3N4), germanium-fluorine compounds (GFn, wherein n=1, 2, or 3), and other germanium-containing compounds. The method may also comprise causing the ion beam to impact a semiconductor wafer.
    Type: Application
    Filed: April 10, 2007
    Publication date: May 8, 2008
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Edwin A. Arevalo, Christopher R. Hatem, Anthony Renau, Jonathan Gerald England
  • Publication number: 20080090392
    Abstract: A technique for improved damage control in plasma doping (PLAD) ion implantation is disclosed. According to a particular exemplary embodiment, the technique may be realized as a method for improved damage control in plasma doping (PLAD) ion implantation. The method may comprise placing a wafer on a platen in a chamber. The method may also comprise generating a plasma in the chamber. The method may additionally comprise implanting at least a portion of ions produced from the plasma into the wafer, wherein the wafer is cooled to a temperature no higher than 0° C during ion implantation, and wherein a dose rate associated with the portion of ions is at least 1×1013 atoms/cm2/second.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 17, 2008
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Vikram Singh, Edwin A. Arevalo, Anthony Renau
  • Publication number: 20080044257
    Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise a platen to hold a wafer in a single-wafer process chamber during ion implantation, the platen including: a wafer clamping mechanism to secure the wafer onto the platen and to provide a predetermined thermal contact between the wafer and the platen, and one or more heating elements to pre-heat and maintain the platen in a predetermined temperature range above room temperature. The apparatus may also comprise a post-cooling station to cool down the wafer after ion implantation. The apparatus may further comprise a wafer handling assembly to load the wafer onto the pre-heated platen and to remove the wafer from the platen to the post-cooling station.
    Type: Application
    Filed: June 28, 2007
    Publication date: February 21, 2008
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan Gerald ENGLAND, Richard Stephen Muka, Edwin A. Arevalo, Ziwei Fang, Vikram Singh
  • Patent number: 7026229
    Abstract: A method and system to achieve shallow junctions using Electromagnetic Induction Heating (EMIH) that can be preceded or followed by a low-temperature Rapid Thermal Annealing (RTA) process. The methods and systems can use, for example, RF or microwave frequencies to induce electromagnetic fields that can induce currents to flow within the silicon wafer, thus causing ohmic collisions between electrons and the lattice structure that heat the wafer volumetrically rather than through the surface. Such EMIH heating can activate the dopant material. Defects in the silicon structure can be repaired by combining the EMIH annealing with a low-temperature (approximately 500–800 degrees Celsius) RTA that causes minimal diffusion, thus minimizing the difference between the as-implanted junction depth and the post-annealing junction depth when compared to annealing methods that only use traditional RTA.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: April 11, 2006
    Assignee: Vartan Semiconductor Equipment Associates, Inc.
    Inventors: Daniel F. Downey, Edwin A. Arevalo
  • Publication number: 20040235281
    Abstract: Disclosed are methods and systems that include doping a semiconductor with at least one dopant, and exposing the semiconductor to an optical source(s), where the exposing occurs before, during, and/or after an annealing stage of said semiconductor. The annealing stage can include an annealing phase and/or an activation phase, which can occur substantially simultaneously. The systems can include at least one doping device for providing at least one dopant to a semiconductor, at least one annealing device to perform an annealing stage, and at least one optical source, where the semiconductor is exposed to light from the optical source(s) before, during, and/or after the annealing stage.
    Type: Application
    Filed: April 26, 2004
    Publication date: November 25, 2004
    Inventors: Daniel F. Downey, Edwin A. Arevalo, Reuel B. Liebert
  • Publication number: 20030186519
    Abstract: A method for forming a junction in a semiconductor by implanting a dopant and an ionic species in the semiconductor, and subjecting the semiconductor to athermal annealing. The athermal annealing, e.g., Electromagnetic Induction Heating (EMIH), can be performed using a microwave and/or RF frequency source. The dopant and the ionic species implantation can be performed simultaneously, the dopant implantation can precede the ionic species implantation, and the ionic species implantation can precede the dopant implantation. The implantation can occur using beam-line implantation or Plasma Doping (PLAD), and techniques such as preamorphized implantation (PAI) can optionally be used. A rapid thermal annealing (RTA) or low temperature rapid thermal annealing (LTRTA) process can also be applied to the semiconductor after implantation. The method can include controlling the oxygen content during the athermal (e.g., EMIH) annealing and/or other annealing (RTA and/or LTRTA) process.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 2, 2003
    Inventors: Daniel F. Downey, Edwin A. Arevalo
  • Publication number: 20030157813
    Abstract: A method and system to achieve shallow junctions using Electromagnetic Induction Heating (EMIH) that can be preceded or followed by a low-temperature Rapid Thermal Annealing (RTA) process. The methods and systems can use, for example, RF or microwave frequencies to induce electromagnetic fields that can induce currents to flow within the silicon wafer, thus causing ohmic collisions between electrons and the lattice structure that heat the wafer volumetrically rather than through the surface. Such EMIH heating can activate the dopant material. Defects in the silicon structure can be repaired by combining the EMIH annealing with a low-temperature (approximately 500-800 degrees Celsius) RTA that causes minimal diffusion, thus minimizing the difference between the as-implanted junction depth and the post-annealing junction depth when compared to annealing methods that only use traditional RTA.
    Type: Application
    Filed: November 28, 2001
    Publication date: August 21, 2003
    Inventors: Daniel F. Downey, Edwin A. Arevalo