Abstract: A method for providing a current path during switching transitions of a switching circuit while limiting the short circuit current. In one embodiment, a switching circuit includes a passive break-before-make element in series with two switches. An alternate embodiment includes a make-before-break element in parallel with the switches. The passive break-before-make element, or make-before-break element, provides a high impedance in a short term and a low impedance in a long term. The switching circuit may be coupled to a load through a low pass filter. In one embodiment, the switching circuit is used in a switching audio amplifier circuit, where correction of nonlinearities incorporates analog feedback to modify the duty ratio of a digitally generated switching signal in the analog domain.

Abstract: A regulation circuit, incorporated in a single integrated circuit with a first circuit load, which as an input coupled to a power supply which produces a source voltage, and a first output coupled to the first circuit load. The regulation circuit comprises an input capacitor for reducing the magnitude of a voltage change at the first output, and at least a first voltage regulator for producing a predetermined voltage at the first load.

Abstract: A method for providing a current path during switching transitions of a switching circuit while limiting the short circuit current. In one embodiment, a switching circuit includes a passive break-before-make element in series with two switches. An alternate embodiment includes a make-before-break element in parallel with the switches. The passive break-before-make element, or make-before-break element, provides a high impedance in a short term and a low impedance in a long term. The switching circuit may be coupled to a load through a low pass filter. In one embodiment, the switching circuit is used in a switching audio amplifier circuit, where correction of nonlinearities incorporates analog feedback to modify the duty ratio of a digitally generated switching signal in the analog domain.

Abstract: A differential amplifier comprises a differential input stage including first and second input devices and has first and second input electrodes and first and second output terminals. A differential load stage includes first and second load devices having first and second control electrodes respectively. The load stage is coupled to the differential input stage and to the first and second output terminals. First and second separate capacitive biasing networks are coupled to the first and second output terminals and respectively to the first and second control electrodes. During an offset-cancellation phase, the input electrodes are coupled to a common voltage. During an amplification phase, a differential input signal is applied to the input electrodes.

Abstract: A single ended input differential output amplifier (100) and integrated circuit including such an amplifier (100). A pair of load resistors (102, 104) are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM. An inductor (106) is connected between input RFIN and a source bias voltage VBS. A first field effect transistor (FET) (108) is connected, drain to source, between load resistor (102) at output OUTP and inductor (106) at RFIN. A second FET (110) is connected, drain to source, between the second load resistor (104) at output OUTM and the source bias voltage VBS. A gate bias voltage VBg is connected to the gate of FET (108) and through resistor (112) to the gate of FET (110). A coupling capacitor (114) is connected between the input RFIN and the gate of FET (110).

Abstract: A voltage regulator 100, 130 for isolating radio frequency circuits from on chip digital circuit originated noise and an integrated circuit chip including the voltage regulator. The voltage regulator 100, 130 includes regulator device (a PFET) 106 driven by a sense amplifier 110 to derive a regulator voltage 108 from a supply voltage 102. Another sense amplifier 114 senses changes in output load and adjusts current flow through a current shunt 120, 122 so that the current shunt 120, 122 shunts excess load current. The sense amplifier 110 driving the voltage regulator device 106 senses current flow through the current shunt 120, 122 and adjusts the current supplied by the regulator device 106 to reduce excess current. The current shunt 120, 122 is a series connected PFET 120 and NFET diode 122, with the gate of the PFET 120 driven to control current flow.

Abstract: Power reception circuits employable in portable data devices (e.g., smart cards) to derive power and/or data from an input AC power signal (e.g., an ASK modulated carrier signal). In one embodiment, the power reception circuit comprises a power rectifier (120), a shunt rectifier (142) and a shunting element (132). The power rectifier (120) is adapted to rectify the input power signal, yielding a rectified output waveform. The shunt rectifier (142) is connected in parallel with the power rectifier (120). The shunting element (132) is connected to the shunt rectifier (142) and is operable to regulate an output voltage or current waveform produced at the output of the power rectifier (120). In another embodiment, the power reception circuit includes an analog circuit (610) for recovering data from a modulated carrier signal. A decoupling device (630) isolates the analog circuit (610) from impedance variations of a load. A shunt device (640) diverts undesired current from the load.

Abstract: A level detector detects an input signal level. A rectifier (210) receives the input signal and provides a rectified signal. A prefilter (220) receives the rectified signal and attenuates high frequency components at frequencies near multiples of a decimation sample rate. The prefiltered signal is decimated (230) and low pass filtered by a lowpass filter (240) having a passband below the input frequency of the input signal. The level detector can be provided to control a variable gain stage circuit (935, 1010) which applies a gain to the input signal based on the level to form a dynamic range compressor or expander.

Abstract: A portable data device employs an integrated circuit having a signal processor that receives a power signal from an external source via a power node. A decoupling device is placed between the power node and the signal processor. An energy reservoir is placed in parallel with the signal processor, which acts in concert with the decoupling device to isolate the effects of the signal processor from the rest of the integrated circuit.

Abstract: An unbuffered flip-flop includes feedback control circuitry providing adaptive control of the internal node during the transfer and latching phases of the flip-flop to prevent back-writing. A complementary pair of transmission gates controlled by the output node are included in the feedback path between an output buffer and a feedback buffer. As noise voltage variations and spikes alter the voltage on the output node, the charge transmittance of the transmission gates is weakened or shut off, thereby preventing the incorrect logic state from being driven by the feedback buffer through to the input of the flip-flop's output buffer and causing back writing. Because the transmission gate transistors are complementary, one transistor or the other will be operating in a transmissive state for each of the bi-stable states of the output buffer during static operation of the flip-flop.

Abstract: An addressable serial test system employs a serial register with parallel outputs. Data is clocked into the serial register via a shift clock signal. A decoder is connected to a portion of the shift register's outputs and provides a selection signal dependent on the data clocked into the serial register. A system clock generates a system clock signal. A storage element includes a clock input coupled to the system clock signal, a data input, an output, a load input coupled to the selection signal, and a test data input coupled to another portion of the shift register's outputs. The storage element's output is alternately forced to a state indicative of the test data input by the selection signal and forced to a state indicative of the data input by the system clock. Structure is included to configure the serial register to read the contents of the storage element.

Abstract: An efficient method and apparatus of median filtering includes a memory circuit (305) for holding a list of N data samples (109). A grading circuit (309, 321, 313, 311) identifies a first data sample of the N data samples that has a first metric with a magnitude less than or equal to (N-1)/2, and a second metric with a magnitude greater than or equal to (N-1)/2. The first metric is indicative of a quantity of data samples, exclusive of the first data sample, that have a magnitude less than a magnitude of the first data sample. The second metric is indicative of a quantity of data samples, exclusive of the first data sample, that have a magnitude less than or equal to the magnitude of the first data sample.

Abstract: A collapsible sawhorse bracket comprising a main member coupled to the sawhorse cross beam, a first leg member pivotally coupled to the main member and coupledto a sawhorse leg, and a second leg member pivotally coupled to the main member and coupled to another sawhorse leg. The main member is formed as one-piece with a central portion having depending side walls thereby defining a substantially U-shaped cross section, as are the two leg members. The leg members are pivotally coupled to the main member by a pair of bolts passing through various sets of aligned apertures in the main and leg member side walls. Bores in the main member side walls releasably receive bosses extending from the leg member side walls to releasably lock the leg members in outwardly extending positions.