Patents by Inventor Edwin Arevalo
Edwin Arevalo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11551904Abstract: A system and method that allows higher energy implants to be performed, wherein the peak concentration depth is shallower than would otherwise occur is disclosed. The system comprises an ion source, an accelerator, a platen and a platen orientation motor that allows large tilt angles. The system may be capable of performing implants of hydrogen ions at an implant energy of up to 5 MeV. By tilting the workpiece during an implant, the system can be used to perform implants that are typically performed at implant energies that are less than the minimum implant energy allowed by the system. Additionally, the resistivity profile of the workpiece after thermal treatment is similar to that achieved using a lower energy implant. In certain embodiments, the peak concentration depth may be reduced by 3 ?m or more using larger tilt angles.Type: GrantFiled: September 9, 2020Date of Patent: January 10, 2023Assignee: Applied Materials, Inc.Inventors: Venkataramana R. Chavva, KyuHa Shim, Hans Gossmann, Edwin Arevalo, Scott Falk, Rajesh Prasad
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Publication number: 20220076915Abstract: A system and method that allows higher energy implants to be performed, wherein the peak concentration depth is shallower than would otherwise occur is disclosed. The system comprises an ion source, an accelerator, a platen and a platen orientation motor that allows large tilt angles. The system may be capable of performing implants of hydrogen ions at an implant energy of up to 5 MeV. By tilting the workpiece during an implant, the system can be used to perform implants that are typically performed at implant energies that are less than the minimum implant energy allowed by the system. Additionally, the resistivity profile of the workpiece after thermal treatment is similar to that achieved using a lower energy implant. In certain embodiments, the peak concentration depth may be reduced by 3 ?m or more using larger tilt angles.Type: ApplicationFiled: September 9, 2020Publication date: March 10, 2022Inventors: Venkataramana R. Chavva, KyuHa Shim, Hans Gossmann, Edwin Arevalo, Scott Falk, Rajesh Prasad
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Patent number: 10515802Abstract: A method may include depositing a mask layer on a substrate using physical vapor deposition, wherein an absolute value of a stress in the mask layer has a first value; and directing a dose of ions into the mask layer, wherein the absolute value of the stress in the mask layer has a second value, less than the first value, after the directing the dose.Type: GrantFiled: July 9, 2018Date of Patent: December 24, 2019Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Rajesh Prasad, Tzu-Yu Liu, Edwin Arevalo, Deven Mittal, Somchintana Norasetthekul, Kyuha Shim, Lauren Liaw, Takaski Shimizu, Nobuyuki Sasaki, Ryuichi Muira, Hiro Ito
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Publication number: 20190326116Abstract: A method may include depositing a mask layer on a substrate using physical vapor deposition, wherein an absolute value of a stress in the mask layer has a first value; and directing a dose of ions into the mask layer, wherein the absolute value of the stress in the mask layer has a second value, less than the first value, after the directing the dose.Type: ApplicationFiled: July 9, 2018Publication date: October 24, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Rajesh Prasad, Tzu-Yu Liu, Edwin Arevalo, Deven Mittal, Somchintana Norasetthekul, Kyuha Shim, Lauren Liaw, Takaski Shimizu, Nobuyuki Sasaki, Ryuichi Muira, Hiro Ito
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Patent number: 8450193Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise a platen to hold a wafer in a single-wafer process chamber during ion implantation, the platen including: a wafer clamping mechanism to secure the wafer onto the platen and to provide a predetermined thermal contact between the wafer and the platen, and one or more heating elements to pre-heat and maintain the platen in a predetermined temperature range above room temperature. The apparatus may also comprise a post-cooling station to cool down the wafer after ion implantation. The apparatus may further comprise a wafer handling assembly to load the wafer onto the pre-heated platen and to remove the wafer from the platen to the post-cooling station.Type: GrantFiled: June 28, 2007Date of Patent: May 28, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Jonathan Gerald England, Richard Stephen Muka, Edwin A. Arevalo, Ziwei Fang, Vikram Singh
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Patent number: 7927986Abstract: A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate in the plasma chamber is biased so that the desired dopant ions impact the substrate with a desired ion energy, thereby implanting the desired dopant ions and the heavy fragments of precursor dopant molecule into the substrate, wherein at least one of the ion energy and composition of the dopant heavy halogenide compound is chosen so that the implant profile in the substrate is substantially determined by the desired dopant ions.Type: GrantFiled: July 22, 2008Date of Patent: April 19, 2011Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, George D. Papasouliotis, Edwin Arevalo
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Publication number: 20100022076Abstract: A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate in the plasma chamber is biased so that the desired dopant ions impact the substrate with a desired ion energy, thereby implanting the desired dopant ions and the heavy fragments of precursor dopant molecule into the substrate, wherein at least one of the ion energy and composition of the dopant heavy halogenide compound is chosen so that the implant profile in the substrate is substantially determined by the desired dopant ions.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, George D. Papasouliotis, Edwin Arevalo
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Patent number: 7642150Abstract: Techniques for forming shallow junctions are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for forming shallow junctions. The method may comprise generating an ion beam comprising molecular ions based on one or more materials selected from a group consisting of: digermane (Ge2H6), germanium nitride (Ge3N4), germanium-fluorine compounds (GFn, wherein n=1, 2, or 3), and other germanium-containing compounds. The method may also comprise causing the ion beam to impact a semiconductor wafer.Type: GrantFiled: April 10, 2007Date of Patent: January 5, 2010Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Edwin A. Arevalo, Christopher R. Hatem, Anthony Renau, Jonathan Gerald England
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Publication number: 20080318345Abstract: An approach that determines an ion implantation processing characteristic in a plasma ion implantation of a substrate is described. In one embodiment, there is a light source configured to direct radiation onto the substrate. A detector is configured to measure radiation reflected from the substrate. A processor is configured to correlate the measured radiation reflected from the substrate to an ion implantation processing characteristic.Type: ApplicationFiled: June 22, 2007Publication date: December 25, 2008Inventors: Harold M. Persing, Vikram Singh, Edwin Arevalo
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Publication number: 20080108208Abstract: Techniques for forming shallow junctions are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for forming shallow junctions. The method may comprise generating an ion beam comprising molecular ions based on one or more materials selected from a group consisting of: digermane (Ge2H6), germanium nitride (Ge3N4), germanium-fluorine compounds (GFn, wherein n=1, 2, or 3), and other germanium-containing compounds. The method may also comprise causing the ion beam to impact a semiconductor wafer.Type: ApplicationFiled: April 10, 2007Publication date: May 8, 2008Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Edwin A. Arevalo, Christopher R. Hatem, Anthony Renau, Jonathan Gerald England
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Publication number: 20080090392Abstract: A technique for improved damage control in plasma doping (PLAD) ion implantation is disclosed. According to a particular exemplary embodiment, the technique may be realized as a method for improved damage control in plasma doping (PLAD) ion implantation. The method may comprise placing a wafer on a platen in a chamber. The method may also comprise generating a plasma in the chamber. The method may additionally comprise implanting at least a portion of ions produced from the plasma into the wafer, wherein the wafer is cooled to a temperature no higher than 0° C during ion implantation, and wherein a dose rate associated with the portion of ions is at least 1×1013 atoms/cm2/second.Type: ApplicationFiled: September 29, 2006Publication date: April 17, 2008Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Vikram Singh, Edwin A. Arevalo, Anthony Renau
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Publication number: 20080044257Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise a platen to hold a wafer in a single-wafer process chamber during ion implantation, the platen including: a wafer clamping mechanism to secure the wafer onto the platen and to provide a predetermined thermal contact between the wafer and the platen, and one or more heating elements to pre-heat and maintain the platen in a predetermined temperature range above room temperature. The apparatus may also comprise a post-cooling station to cool down the wafer after ion implantation. The apparatus may further comprise a wafer handling assembly to load the wafer onto the pre-heated platen and to remove the wafer from the platen to the post-cooling station.Type: ApplicationFiled: June 28, 2007Publication date: February 21, 2008Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Jonathan Gerald ENGLAND, Richard Stephen Muka, Edwin A. Arevalo, Ziwei Fang, Vikram Singh
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Publication number: 20070224840Abstract: A method of selecting plasma doping process parameters includes determining a recipe parameter database for achieving at least one plasma doping condition. The initial recipe parameters are determined from the recipe parameter database. In-situ measurements of at least one plasma doping condition are performed. The in-situ measurements of the at least one plasma doping condition are correlated to at least one plasma doping result. At least one recipe parameter is changed in response to the correlation so as to improve at least one plasma doping process performance metric.Type: ApplicationFiled: March 19, 2007Publication date: September 27, 2007Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Anthony Renau, Vikram Singh, Atul Gupta, Timothy Miller, Edwin Arevalo, George Papasouliotis, Yong Bae Jeon
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Patent number: 7026229Abstract: A method and system to achieve shallow junctions using Electromagnetic Induction Heating (EMIH) that can be preceded or followed by a low-temperature Rapid Thermal Annealing (RTA) process. The methods and systems can use, for example, RF or microwave frequencies to induce electromagnetic fields that can induce currents to flow within the silicon wafer, thus causing ohmic collisions between electrons and the lattice structure that heat the wafer volumetrically rather than through the surface. Such EMIH heating can activate the dopant material. Defects in the silicon structure can be repaired by combining the EMIH annealing with a low-temperature (approximately 500–800 degrees Celsius) RTA that causes minimal diffusion, thus minimizing the difference between the as-implanted junction depth and the post-annealing junction depth when compared to annealing methods that only use traditional RTA.Type: GrantFiled: November 28, 2001Date of Patent: April 11, 2006Assignee: Vartan Semiconductor Equipment Associates, Inc.Inventors: Daniel F. Downey, Edwin A. Arevalo
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Publication number: 20050260838Abstract: A method for activating a first ionic species implanted in a semiconductor, including annealing the semiconductor using a controlled diffusion annealing, and controlling the oxygen content during the annealing to redistribute the first ionic species such that the abruptness of the implanted profile is increased after the annealing.Type: ApplicationFiled: May 9, 2003Publication date: November 24, 2005Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Daniel Downey, Edwin Arevalo
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Publication number: 20040235281Abstract: Disclosed are methods and systems that include doping a semiconductor with at least one dopant, and exposing the semiconductor to an optical source(s), where the exposing occurs before, during, and/or after an annealing stage of said semiconductor. The annealing stage can include an annealing phase and/or an activation phase, which can occur substantially simultaneously. The systems can include at least one doping device for providing at least one dopant to a semiconductor, at least one annealing device to perform an annealing stage, and at least one optical source, where the semiconductor is exposed to light from the optical source(s) before, during, and/or after the annealing stage.Type: ApplicationFiled: April 26, 2004Publication date: November 25, 2004Inventors: Daniel F. Downey, Edwin A. Arevalo, Reuel B. Liebert
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Publication number: 20030186519Abstract: A method for forming a junction in a semiconductor by implanting a dopant and an ionic species in the semiconductor, and subjecting the semiconductor to athermal annealing. The athermal annealing, e.g., Electromagnetic Induction Heating (EMIH), can be performed using a microwave and/or RF frequency source. The dopant and the ionic species implantation can be performed simultaneously, the dopant implantation can precede the ionic species implantation, and the ionic species implantation can precede the dopant implantation. The implantation can occur using beam-line implantation or Plasma Doping (PLAD), and techniques such as preamorphized implantation (PAI) can optionally be used. A rapid thermal annealing (RTA) or low temperature rapid thermal annealing (LTRTA) process can also be applied to the semiconductor after implantation. The method can include controlling the oxygen content during the athermal (e.g., EMIH) annealing and/or other annealing (RTA and/or LTRTA) process.Type: ApplicationFiled: April 1, 2002Publication date: October 2, 2003Inventors: Daniel F. Downey, Edwin A. Arevalo
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Publication number: 20030157813Abstract: A method and system to achieve shallow junctions using Electromagnetic Induction Heating (EMIH) that can be preceded or followed by a low-temperature Rapid Thermal Annealing (RTA) process. The methods and systems can use, for example, RF or microwave frequencies to induce electromagnetic fields that can induce currents to flow within the silicon wafer, thus causing ohmic collisions between electrons and the lattice structure that heat the wafer volumetrically rather than through the surface. Such EMIH heating can activate the dopant material. Defects in the silicon structure can be repaired by combining the EMIH annealing with a low-temperature (approximately 500-800 degrees Celsius) RTA that causes minimal diffusion, thus minimizing the difference between the as-implanted junction depth and the post-annealing junction depth when compared to annealing methods that only use traditional RTA.Type: ApplicationFiled: November 28, 2001Publication date: August 21, 2003Inventors: Daniel F. Downey, Edwin A. Arevalo