Abstract: Techniques are provided herein to form semiconductor dies with a thermally conductive bond interface to enhance the thermal dissipation from the semiconductor devices. A frontside interconnect region is provided above a semiconductor device layer to, for example, route signals between various semiconductor devices in the device layer. A thermally conductive bond layer may be provided above the frontside interconnect region, such as on a top-most layer of the frontside interconnect region. The thermally conductive bond layer includes a metal such as titanium, ruthenium, copper, or generally any material having a thermal conductivity of at least 1.5 W/m·K. The bond layer may be formed on a material layer that is deposited first on the frontside interconnect region. The material layer may be any of diamond, silicon carbide, copper, or aluminum nitride, to name a few examples.

Abstract: Techniques are provided herein to form semiconductor devices with thermal management structures designed to provide additional heat dissipation paths. A semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. In one example, a subfin region beneath the semiconductor region is removed and replaced with a material having a thermal conductivity of at least 1.5 W/m·K. In another example, a material layer is formed between conductive contacts on the top surfaces of the source and drain regions that has a thermal conductivity of at least 1.5 W/m·K. In another example, the conductive contacts extend through at least 50% of an entire height of the source and drain regions to provide an enhanced thermal path. Any of the above-mentioned structures may also be combined in one or more devices to provide multiple different thermal management structures.

Abstract: Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.