Abstract: A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.

Abstract: A chip package includes a circuit board having a first surface with an inner die-attach region, an outer signal trace region and an intermediate utility region. Within the utility region are a number of traces for providing fixed electrical potentials to an integrated circuit die mounted within the die-attach region. In the preferred embodiment, the utility region includes a ring-like ground trace, a V.sub.DD trace and a segmented outer trace, with the segments of the segmented trace being connected to at least two fixed voltages for operating the integrated circuit die. Bond wires or leads of a leadframe include inner wire/lead ends connected to input/output pads of the die and include outer wire/lead ends connected to either a trace or trace segment in the utility region or a signal trace located in the outer signal trace region. The resulting chip package may be of the ball grid array type.

Abstract: The present invention relates to a substrate for ball-grid arrays. Bond sites are arranged around a die-attach region of the substrate. Signal traces connect the bond sites to vias disposed on the substrate, thus providing an electrical path between both sides of the substrate. Solder balls (solder bumps) are disposed on the other side of the substrate and arranged in a grid-like pattern. The generally linearly-arranged bond sites are sequentially numbered, as is the grid-like arrangement of solder balls. In a preferred embodiment, the bond sites are used only for carrying signals to and from the semiconductor die. In addition, only the solder bumps used for carrying signals are sequentially numbered. In another embodiment of the invention, some of the bond sites may be used for utilities such as ground and power. Such utility bond sites are not numbered. Likewise, utility solder balls are not numbered. The signal bond sites are coupled to vias by signal traces.

Abstract: A semiconductor die attach arrangement which provides an increase in signal availability to and from the die without compromising the physical integrity of signal traces and integrity of the conducted signal. In a preferred embodiment, a circuit board includes a die-attach region surrounded by a boundary line that is spaced apart from the die-attach region, thereby defining an intermediate region which surrounds the die-attach region. Bond sites are arranged along the boundary line. In one embodiment, the bond sites are first trace ends of a plurality of signal traces, some of the signal traces extending in an outward direction away from the die-attach region into a signal trace region, and some of the signal traces being directed within the intermediate region. Signal vias are formed in both the signal trace region and the intermediate region, and are electrically coupled to the signal traces at second trace ends of the signal traces.

Abstract: A multi-voltage circuit on a semiconductor chip including core circuitry driven by a power supply voltage equal to the voltage of a selected external device operating in connection with the semiconductor chip, and having input/output circuitry in selected regions for operating in connection with external devices having the same operating voltage and other external devices having a selected substantially lower operating voltage. Peripheral input/output circuit regions of at least first and second kinds are established for interfacing with the respective high and low voltage external devices. According to one version of the invention, the input/output circuitry directed toward interfacing with external devices operating at a particular voltage level is concentrated at a particular peripheral region in the periphery of the semiconductor chip. According to another version of the invention, multiple regions of input/output circuitry are established for external devices at the same voltage level.