Abstract: The present inventions provide apparatuses and methods for implementing a programmable bus. A programmable bus provides greater functionality and versatility through the ability to manage data transfers according to a number of sample rate clocks. The number of processing components connected to the programmable bus may be varied without a significant amount of physical alternations. Also, the number of data transfers for a given number of processing components may be modified and scheduled accordingly by reprogramming the programmable bus. The programmable bus comprises a bus and a bus arbiter. The bus is coupled to the bus arbiter and a plurality of devices and the bus arbiter. The plurality of devices operate at different sample rate clocks. The bus arbiter schedules and conducts the transfer of data between the plurality of devices according to the sample rate clocks such that the plurality of devices send and receive data at appropriate times, corresponding to the sample rate clocks.