Abstract: An ASCII-based processing system is disclosed. A memory is divided into a plurality of logical partitions. Each partition has a range of memory addresses and includes information associated with a particular task. Task information includes contents of task state register and one or more task data registers, with each task data register having an ASCII name. Each task data register is successively labeled with a unique alphabetic character label starting with the character ‘A.’ A dataflow unit within the processing system is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task. Task instructions can include ASCII characters that indicate a request for resources and indicate the ASCII-character designated names of task data registers on which the task instruction operates. A processing element receiving the task instruction performs the operation indicated by the ASCII operator code on the indicated task data registers.

Abstract: An ASCII-based processing system is disclosed. A memory is divided into a plurality of logical partitions. Each partition has a range of memory addresses and includes information associated with a particular task. Task information includes contents of task state register and one or more task data registers, with each task data register having an ASCII name. Each task data register is successively labeled with a unique alphabetic character label starting with the character ‘A.’ A dataflow unit within the processing system is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task. Task instructions can include ASCII characters that indicate a request for resources and indicate the ASCII-character designated names of task data registers on which the task instruction operates. A processing element receiving the task instruction performs the operation indicated by the ASCII operator code on the indicated task data registers.

Abstract: An ASCII-based processing system is disclosed. A memory is divided into a plurality of logical partitions. Each partition has a range of memory addresses and includes information associated with a particular task. Task information includes contents of task state register and one or more task data registers, with each task data register having an ASCII name. Each task data register is successively labeled with a unique alphabetic character label starting with the character ‘A.’ A dataflow unit within the processing system is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task. Task instructions can include ASCII characters that indicate a request for resources and indicate the ASCII-character designated names of task data registers on which the task instruction operates. A processing element receiving the task instruction performs the operation indicated by the ASCII operator code on the indicated task data registers.

Abstract: System and method for interpreting ASCII code fetched from a code space of a task partition that is part of memory shared by a host processor and a multitask controller (MTC). The MTC includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The shared memory also includes a system partition containing a code space. The fetched code is monitored for adjacent ASCII alphabetic characters and if at least two are found and the fetched code is terminated by an ASCII space character, the code table in the code space of the system partition is scanned to find a command that matches the fetched code. The byte in the table immediately following the matched fetched code and having a bit set indicating that it is interpreted is obtained and written over the ASCII space character in the code space of the task partition.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller. In one embodiment, the path between the resource manager and the processing elements is the same for all processing elements. In another embodiment, the data path is different between different processing elements. A processing element receives a request via a strobe signal and data on a path between the resource manager and the processing element and reports status on the data path via a different strobe signal. The request to the processing element may specify floating point computations, as well as sorting operations. The processing element can use an auxiliary memory to aid in the sorting operations. Push and pop functions are processed by the processing element to facilitate the loading of multiple data operands in the processing element.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller. The memory is organized into a set of logical partitions. Task partitions describe a task and include task state information, task data registers and ASCII task instructions. The task state information includes a set of index registers that are accessible by the task instructions. The index registers typically have dedicated locations in the task partition and are referred to by lower case ASCII alphabetic characters. Index registers are used to refer to a task partition in some cases or to a location in the current task partition in other cases for purposes of branching. Index registers can be incremented or decremented and loaded with an immediate data value. In one embodiment, the data flow unit is used to interpret the branch code and fetch contents of a named index register used in the branch.

Abstract: The disclosure describes a computing system having one or more processing elements, one of which is a floating point processor, a memory, and a multitask controller. The multitask controller includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The memory has two interfaces. One interface connects to a host processor and the other interface connects to the data flow unit of the controller so that the memory appears intelligent. The resource manager in the controller finds a processing element, such as a floating point element, that is available to perform a function for a task and assigns it to a task. The scheduler unit selects a task and an assigned processing element to carry out the function of the cuffent task, the results of which are placed back in the memory.

Abstract: A wakeup mechanism for computing system is disclosed. A wakeup unit connected to a host interface is configured to detect a sequence of data values and to generate the activation signal if the detected sequence matches an expected sequence of data values. First, a read by the host processor at a particular address in memory is detected by the wakeup unit. Next, a sequence of data values is written to the address by the host processor and the wakeup unit compares the sequence to an expected sequence. If there is a match, the wakeup unit causes the multitasking controller to execute a test of the data in memory. If the test is positive, then an indicator is written to the address and when the host reads the indicator, the wakeup unit causes the multitask controller to become active.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The memory has an interface that includes a task page mechanism with an index register. A portion of the multi-task controller also has a task page register for accessing the memory via another interface. The task page mechanism provides access to the memory by the host processor. The index register can be loaded by either the address or data bus of the host processor. In one embodiment, the task page mechanism includes a comparator and a counter to facilitate a polling scan of the status of the various tasks in the memory.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The computing system operates on ASCII instructions which includes a set of ASCII operators. The operators include both ASCII data operators and ASCII system operators. The system operators include characters for specifying a request to obtain resources, to perform a task switch, to perform a task suspension, to execute a branch, to transfer results of an operation into a task data register, to transfer data into a processing element, to record the current location of instruction execution in the task code space, to treat a sequence of symbols as a group, and to perform an output function. Data operators include characters for specifying a request to perform arithmetic and logical operations on data.

Abstract: A computing system that includes one or more processing elements, a memory connected to a host processor and a multitask controller, where the multitask controller includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The processing elements, the scheduler unit, the data flow unit, the executive unit, and the resource manager unit are each synchronously clocked by a clock signal. The processing elements, multitask controller interface of the memory, the executive unit, and the scheduler unit are each operative to change one or more interface signals on a positive transition of the clock signal while the resource manager unit and dataflow unit are each operative to change one or more interface signals on a negative transition of the clock signal. Because adjacent units are clocked on opposite edges, the speed of transfer of information between the units is improved.

Abstract: A variable task size architecture is disclosed. A system partition is included that is dedicated to system use. The system partition contains a number of specifiers that describe the number of tasks in the system memory, and for each task partition, the location and size of a task status register, the number, location and size of each of a set of task data registers, and the size and starting location of task code. Specifiers include the word size in bytes, the number of words per increment, the number of increments per partition, the number of increments per data register, and the number of data registers. In one embodiment, the number of tasks is available from an input port. The task specifiers and the number of tasks are accessible to the scheduler unit via the data flow unit when a reset signal is released.

Abstract: Coordination between multiple processors presents a set of difficult problems, since most processors are not designed for multi-processing, but for multi-tasking. Additionally, CPUs are increasingly limited by the memory bandwidth bottleneck. The iMEM architecture addresses the multi-processing problem, by simplifying processor access, and the memory bandwidth problem, by distributing intelligence across the memory system. ASCII encoding of task structure and instructions addresses compiler complexities.

Abstract: A table driven call management system for an organization having a plurality of departments and agent. The call management system is capable of supporting local and remote agents each of which can have the same degree of access to the organization's information. Calls are received by the call management system and handled according to a table describing a department in the organization. If an agent for the department is available according to the table, the call is transferred to the agent, either local or remote. If the agent is not available, the call is transferred to another department according to an entry in the table. If no department has an agent available to take the call, a caller message is recording in a department mailbox or a default mail box or the call is transferred to an available operator.

Abstract: A selection system for configuring a device controller. The selection system includes a plurality of state machines each of which has a portion of the configuration information needed to inform a host, connected to the device controller via a serial bus, of the device configuration as well as the configuration, interface and endpoint information. The selection system also includes a selection circuit that selects one of the plurality of state machines in response to a selection code that can be set by a user manually or automatically by programming are register. The manual setting of the selection code is by means of a set of configurable pins which are selected as the default source of the selection code by the selection system.

Abstract: An apparatus and method of measuring the performance of a computer network by determining transit times of packets between two selected sites connected by the computer network and the public switched telephone network and deriving from those transit times a measure of the performance of the computer network. Software establishes a network connection and a circuit switched connection between the two selected sites. A pair of messages is sent, at the same or nearly the same time, over the network connection and the circuit-switched connection and the transit time for a one way trip over the network connection is derived from the trips over the network and circuit-switched connections. This furnishes a measurement from which performance statistics of the computer network can be derived.

Abstract: A device controller for connecting a function engine that supports an application to a packet-switched serial bus to which a host device is connected. The interface device includes a serial interface engine for transferring packets between the serial bus and the function engine and an interfacing device that employs a plurality of state machines in a device configuration module. The state machines of the device configuration module operate to configure the interfacing device and make that configuration known to the host. Additionally, for each interface of the function engine that is a group of state machines, at least one of which transfers data between the serial interface engine and the function engine. In one embodiment the serial bus is the USB and the configuration module conforms to the configuration protocol of the USB. As an additional aspect of the invention multiple configurations are supported by the device configuration module.

Abstract: A system is described capable of excising individual cells in an N-dimensional array and healing the array connectivity without manual intervention. Thus cells that fail can be deleted and the array remain viable, although possibly requiring re-synchronization procedures to be performed. The system allows either replacement of bad cells or bypassing of bad cells, with appropriate cost and operational differences. Both level sensitive and edge sensitive excision mechanisms are described and the consequences of each discussed. The invention applies to processor arrays with one cell per physical chip or many cells per chip, and handles uni-directional or bi-directional data flows, and is generally both interface independent and technology independent.

Abstract: A system for extending standard processors using either undefined op-codes or sparse address spaces to maintain the use of legacy processor tools and reduce the complexity of the design process. The disclosure describes a method and apparatus for adding circuitry to processing units that allows partitioning of the design into a fixed processing unit derivative and a configurable subsystem. The legacy processor unit language tools work with the fixed processing unit derivative while the logic design tools work well with the configurable subsystem. In one embodiment, the configurable subsystem is implemented with easily available programmable Logic Devices (PLD's and FPGA's).

Abstract: A method for controlling the execution of a sole target processor or a target processor embedded in a chain of target processor units by a host-processor. The target processor unit includes a shared control register, a shared memory accessible by both the target and host processor and a code memory alterable by the host processor and containing the target processor program. The shared control register includes a single step flag to indicate that the host processor is setting the single step mode of operation for the target processor. The shared control register further includes a clock inhibit flag to permit the target processor to stop execution. Clearing the clock inhibit flag releases the target processor to execute the program in the code memory during which the target processor tests the single step flag to determine whether it should stop execution after one instruction has been executed.