Patents by Inventor Edwin E. Parks

Edwin E. Parks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10198333
    Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: February 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Brian Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
  • Publication number: 20150127983
    Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.
    Type: Application
    Filed: December 23, 2010
    Publication date: May 7, 2015
    Applicant: INTEL CORPORATION
    Inventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Briar Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
  • Patent number: 6377278
    Abstract: A computer-implemented method and associated apparatus for generating digital map images of a uniform format. Bit-mapped map images corresponding to a printed map are obtained by scanning or other means. A bit-mapped map image is then cropped to select a map image corresponding to a desired geographic area, such as a one-degree by one-degree area. The boundaries of the selected map image are moved to shape the geographic area into a tessellated shape, such as a rectangle. The selected map image is then re-sized to contain a predetermined pixel area. The map image, now of a uniform format, is then stored with an identifier of a reference point and size of the geographic area represented by the map image. The identifier may be the name of a computer-readable file containing the map image.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: April 23, 2002
    Assignee: Amesmaps, LLC
    Inventors: William Ames Curtright, Edwin E. Parks, Kevin J. Roethe, Matthew T. Bieker
  • Patent number: 6199015
    Abstract: A navigation system includes a processor and bit-mapped earth surface map image data in a first data storage device accessed by the processor/, the processor displaying an image essentially filling a display area of a display screen and centered on any latitude and longitude supplied to the processor, the image having no discontinuities. The processor may receive latitude and longitude inputs from a user via a user input device, or from a global positioning system (GPS) receiver incorporated in the navigation system. The displayed map image may thus be centered at a desired longitude and latitude or at the longitude and latitude of the navigation system itself. The system may include a second data storage device for storing data from and providing data to the processor. Route information such as flight plan data may then be stored in the second data storage device.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: March 6, 2001
    Assignee: Ames Maps, L.L.C.
    Inventors: William Ames Curtwright, Edwin E. Parks
  • Patent number: 5884219
    Abstract: A navigation system includes a processor and bit-mapped earth surface map image data in a first data storage device accessed by the processor, the processor displaying an image essentially filling a display area of a display screen and centered on any latitude and longitude supplied to the processor, the image having no discontinuities. The processor may receive latitude and longitude inputs from a user via a user input device, or from a global positioning system (GPS) receiver incorporated in the navigation system. The displayed map image may thus be centered at a desired longitude and latitude or at the longitude and latitude of the navigation system itself. The system may include a second data storage device for storing data from and providing data to the processor. Route information such as flight plan data may then be stored in the second data storage device.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: March 16, 1999
    Assignee: Ames Maps L.L.C.
    Inventors: William Ames Curtwright, Edwin E. Parks
  • Patent number: 5844570
    Abstract: A computer-implemented method and associated apparatus for generating digital map images of a uniform format. Bit mapped map images corresponding to a printed map are obtained by scanning or other means. A bit mapped map image is then cropped to select a map image corresponding to a desired geographic area, such as a one degree by one degree area. The boundaries of the selected map image are moved to shape the geographic area into a tessellated shape, such as a rectangle. The selected map image is then re-sized to contain a predetermined pixel area. The map image, now of a uniform format, is then stored with an identifier of a reference point and size of the geographic area represented by the map image. For example, the identifier may be the name of a computer-readable file containing the map image.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: December 1, 1998
    Assignee: Ames Research Laboratories
    Inventors: William Ames Curtright, Edwin E. Parks, Kevin J. Roethe, Matthew T. Bieker