Patents by Inventor Edwin Goh

Edwin Goh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Control of electrolyte hydrodynamics for efficient mass transfer during electroplating
    Patent number: 9394620
    Abstract: Described are apparatus and methods for electroplating one or more metals onto a substrate. Embodiments include electroplating apparatus configured for plating highly uniform metal layers. In specific embodiments, the apparatus includes a flow-shaping element made of an ionically resistive material and having a plurality of channels made through the flow shaping element. The channels allow for transport of the electrolyte through the flow shaping element during electroplating. The channel openings are arranged in a spiral-like pattern on the substrate-facing surface of the flow shaping element such that the center of the spiral-like pattern is offset from the center of the flow shaping element.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: July 19, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter, Edwin Goh, Bryan L. Buckalew, Robert Rash
  • CONTROL OF ELECTROLYTE HYDRODYNAMICS FOR EFFICIENT MASS TRANSFER DURING ELECTROPLATING
    Publication number: 20140299477
    Abstract: Described are apparatus and methods for electroplating one or more metals onto a substrate. Embodiments include electroplating apparatus configured for plating highly uniform metal layers. In specific embodiments, the apparatus includes a flow-shaping element made of an ionically resistive material and having a plurality of channels made through the flow shaping element. The channels allow for transport of the electrolyte through the flow shaping element during electroplating. The channel openings are arranged in a spiral-like pattern on the substrate-facing surface of the flow shaping element such that the center of the spiral-like pattern is offset from the center of the flow shaping element.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 9, 2014
    Inventors: Steven T. Mayer, David W. Porter, Edwin Goh, Bryan L. Buckalew, Robert Rash
  • Intermetal dielectric layer for integrated circuits
    Patent number: 6528886
    Abstract: An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: March 4, 2003
    Assignees: Chartered Semiconductor Manufacturing LTD, Lucent Technologies
    Inventors: Huang Liu, John Sudijono, Juan Boon Tan, Edwin Goh, Alan Cuthbertson, Arthur Ang, Feng Chen, Qiong Li, Peter Chew
  • Intermetal dielectric layer for integrated circuits
    Publication number: 20020130418
    Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
    Type: Application
    Filed: April 29, 2002
    Publication date: September 19, 2002
    Inventors: Huang Liu, John Sudijono, Juan Boon Tan, Edwin Goh, Alan Cuthbertson, Arthur Ang, Feng Chen, Qiong Li, Peter Chew
  • Intermetal dielectric layer for integrated circuits
    Patent number: 6451687
    Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: September 17, 2002
    Assignees: Chartered Semiconductor Manufacturing Ltd., Lucent Technologies Inc.
    Inventors: Huang Liu, John Sudijono, Juan Boon Tan, Edwin Goh, Alan Cuthbertson, Arthur Ang, Feng Chen, Qiong Li, Peter Chew