Patents by Inventor Edwin J. Pole, II

Edwin J. Pole, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7069456
    Abstract: A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: June 27, 2006
    Assignee: Intel Corporation
    Inventors: David S. Bormann, Chao-Hsin Chi, Frank P. Hart, Edwin J. Pole, II, Dong Tieu
  • Patent number: 6795896
    Abstract: A method of reducing power leakage consumption in a processor by shutting off power to the cache memory when the processor is idle. The contents of the cache memory are written to a low leakage memory such as SDRAM or main memory. The power to the cache memory is then cut off and remains off until the occurrence of a system event. While power to the cache memory remains off, the cache memory interface is left operational so that the portion of the cache memory image stored in other memory is marked invalid if the corresponding data in main memory has been modified. Upon the occurrence of the system event the cache memory contents are automatically restored to the cache memory within a specified time.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Frank Hart, Edwin J. Pole, II
  • Patent number: 6675304
    Abstract: A voltage regulator may switch in an extra load when the voltage regulator changes from a higher to a lower output level in response to a processor change of state in a processor-based system. The additional load at the lower voltage level in the processor-based system may decrease the latency in the voltage level transistor, improving processor performance.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventors: Edwin J. Pole, II, Scott R. Rushford
  • Patent number: 6496888
    Abstract: A method for incorporating bus ratio strap options in chipset logic. The method of one embodiment first fabricates a register and multiplexer in chipset logic. The register is programmed with a bus ratio setting. A bus ratio setting is selected to be the output from the multiplexer. The selected bus ratio setting is driven out from the multiplexer to output pins.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: December 17, 2002
    Assignee: Intel Corporation
    Inventor: Edwin J. Pole, II
  • Patent number: 6311281
    Abstract: A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: October 30, 2001
    Inventors: Edwin J. Pole, II, John T. Orton, Cau L. Nguyen, Gurbir Singh, Xia Dai, Ravi Nagaraj
  • Patent number: 6272642
    Abstract: A system includes a component, a detector adapted to detect generation of a power management event, and a controller adapted to transition the component from a first performance mode to a lower activity state in response to the power management event. The controller is adapted to change a setting of the component to a second, different performance mode while the component is in the lower activity state. The power management event may be generated in response to a change in the system's power source, an over-temperature condition, or a user command.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: August 7, 2001
    Assignee: Intel Corporation
    Inventors: Edwin J. Pole, II, Scott R. Rushford, Eric S. Swartzendruber, Xia Dai
  • Patent number: 6118306
    Abstract: A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: September 12, 2000
    Assignee: Intel Corporation
    Inventors: John T. Orton, Cau L. Nguyen, Gurbir Singh, Xia Dai, Raviprakash Nagaraj, Edwin J. Pole, II