Abstract: An image sensor that includes a substrate including a pixel array area and a dummy pixel area surrounding the pixel array area; a plurality of photodiodes within the substrate; a pixel separation pattern between the plurality of photodiodes; a light blocking pattern overlapping at least one of the plurality of photodiodes in the dummy pixel area; a plurality of color filters on the plurality of photodiodes; and a microlens layer on the plurality of color filters and the light blocking pattern, the microlens layer including a flat portion and a plurality of microlenses. In the dummy pixel area the flat portion of the microlens layer overlaps the light blocking pattern, the plurality of microlenses are spaced apart with the flat portion interposed between microlenses of the plurality of microlenses, and the microlenses are on the plurality of color filters.

Abstract: A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.

Abstract: A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.

Abstract: A memory device including a reference voltage (VREF) generator and method for operating the same to improve memory sensing margin, and extend operational temperature range and life of the device are disclosed. Generally, the device further includes an array of non-volatile memory cells divided into a plurality of blocks, a sensing circuit coupled to the array to receive and compare memory signals therefrom to the VREF to read data from the cells. The Local reference voltage generator is configured to provide one of a number of reference voltages to the sensing circuit based on which of the blocks is being read. The array can be divided based on row and column addresses of cells in the blocks. Where the cells include 1T1C ferroelectric random access memory (F-RAM) cells, and the reference voltages are selected based on a lowest P-term or highest U-term of the cells in the block being read.

Abstract: A memory device including a reference voltage (VREF) generator and method for operating the same to improve memory sensing margin, and extend operational temperature range and life of the device are disclosed. Generally, the device further includes an array of non-volatile memory cells divided into a plurality of blocks, a sensing circuit coupled to the array to receive and compare memory signals therefrom to the VREF to read data from the cells. The Local reference voltage generator is configured to provide one of a number of reference voltages to the sensing circuit based on which of the blocks is being read. The array can be divided based on row and column addresses of cells in the blocks. Where the cells include 1T1C ferroelectric random access memory (F-RAM) cells, and the reference voltages are selected based on a lowest P-term or highest U-term of the cells in the block being read.

Abstract: The present disclosure pertains to our discovery that depositing various film layers in a particular order using a combination of Ion Metal Plasma (IMP) and traditional sputter deposition techniques with specific process conditions results in a barrier layer structure which provides excellent barrier properties and allows for metal/conductor filling of contact sizes down to 0.25 micron and smaller without junction spiking. Specifically, the film layers are deposited on a substrate in the following order: (a) a first layer of a barrier metal (M), deposited by IMP sputter deposition; (b) a second layer of an oxygen-stuffed barrier metal (MOx), an oxygen-stuffed nitride of a barrier metal (MNOx), or a combination thereof; (c) a third layer of a nitride of a barrier metal (MNx), deposited by IMP sputter deposition of the barrier metal in the presence of nitrogen; and (d) a fourth, wetting layer of a barrier metal, deposited by traditional sputter deposition.

Abstract: The present disclosure pertains to our discovery that depositing various film layers in a particular order using a combination of Ion Metal Plasma (IMP) and traditional sputter deposition techniques with specific process conditions results in a barrier layer structure which provides excellent barrier properties and allows for metal/conductor filling of contact sizes down to 0.25 micron and smaller without junction spiking. Specifically, the film layers are deposited on a substrate in the following order: (a) a first layer of a barrier metal (M), deposited by IMP sputter deposition; (b) a second layer of an oxygen-stuffed barrier metal (MOx), an oxygen-stuffed nitride of a barrier metal (MNOx), or a combination thereof; (c) a third layer of a nitride of a barrier metal (MN.sub.x), deposited by IMP sputter deposition of the barrier metal in the presence of nitrogen; and (d) a fourth, wetting layer of a barrier metal, deposited by traditional sputter deposition.