Abstract: System and method for interpreting ASCII code fetched from a code space of a task partition that is part of memory shared by a host processor and a multitask controller (MTC). The MTC includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The shared memory also includes a system partition containing a code space. The fetched code is monitored for adjacent ASCII alphabetic characters and if at least two are found and the fetched code is terminated by an ASCII space character, the code table in the code space of the system partition is scanned to find a command that matches the fetched code. The byte in the table immediately following the matched fetched code and having a bit set indicating that it is interpreted is obtained and written over the ASCII space character in the code space of the task partition.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The computing system operates on ASCII instructions which includes a set of ASCII operators. The operators include both ASCII data operators and ASCII system operators. The system operators include characters for specifying a request to obtain resources, to perform a task switch, to perform a task suspension, to execute a branch, to transfer results of an operation into a task data register, to transfer data into a processing element, to record the current location of instruction execution in the task code space, to treat a sequence of symbols as a group, and to perform an output function. Data operators include characters for specifying a request to perform arithmetic and logical operations on data.

Abstract: A variable task size architecture is disclosed. A system partition is included that is dedicated to system use. The system partition contains a number of specifiers that describe the number of tasks in the system memory, and for each task partition, the location and size of a task status register, the number, location and size of each of a set of task data registers, and the size and starting location of task code. Specifiers include the word size in bytes, the number of words per increment, the number of increments per partition, the number of increments per data register, and the number of data registers. In one embodiment, the number of tasks is available from an input port. The task specifiers and the number of tasks are accessible to the scheduler unit via the data flow unit when a reset signal is released.

Abstract: A computing system that includes one or more processing elements, a memory connected to a host processor and a multitask controller, where the multitask controller includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The processing elements, the scheduler unit, the data flow unit, the executive unit, and the resource manager unit are each synchronously clocked by a clock signal. The processing elements, multitask controller interface of the memory, the executive unit, and the scheduler unit are each operative to change one or more interface signals on a positive transition of the clock signal while the resource manager unit and dataflow unit are each operative to change one or more interface signals on a negative transition of the clock signal. Because adjacent units are clocked on opposite edges, the speed of transfer of information between the units is improved.

Abstract: Coordination between multiple processors presents a set of difficult problems, since most processors are not designed for multi-processing, but for multi-tasking. Additionally, CPUs are increasingly limited by the memory bandwidth bottleneck. The iMEM architecture addresses the multi-processing problem, by simplifying processor access, and the memory bandwidth problem, by distributing intelligence across the memory system. ASCII encoding of task structure and instructions addresses compiler complexities.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. One of the processing elements is a floating point element. In one embodiment, the floating point element performs floating point calculations on ASCII data. The floating point element receives data in the form of ASCII character strings that are terminated by an ASCII space character and control information via a strobe that indicates the function to be performed on the data. The functions includes addition, subtraction, multiplication, division, and push and pop. The floating point element performs floating point calculations for a particular task which is indicated by a tag that is stored in the floating point element. Status of a floating point element is available via a read strobe that returns a status byte.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The memory has an interface that includes a task page mechanism with an index register. A portion of the multi-task controller also has a task page register for accessing the memory via another interface. The task page mechanism provides access to the memory by the host processor. The index register can be loaded by either the address or data bus of the host processor. In one embodiment, the task page mechanism includes a comparator and a counter to facilitate a polling scan of the status of the various tasks in the memory.

Abstract: A wakeup mechanism for computing system is disclosed. A wakeup unit connected to a host interface is configured to detect a sequence of data values and to generate the activation signal if the detected sequence matches an expected sequence of data values. First, a read by the host processor at a particular address in memory is detected by the wakeup unit. Next, a sequence of data values is written to the address by the host processor and the wakeup unit compares the sequence to an expected sequence. If there is a match, the wakeup unit causes the multitasking controller to execute a test of the data in memory. If the test is positive, then an indicator is written to the address and when the host reads the indicator, the wakeup unit causes the multitask controller to become active.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller. In one embodiment, the path between the resource manager and the processing elements is the same for all processing elements. In another embodiment, the data path is different between different processing elements. A processing element receives a request via a strobe signal and data on a path between the resource manager and the processing element and reports status on the data path via a different strobe signal. The request to the processing element may specify floating point computations, as well as sorting operations. The processing element can use an auxiliary memory to aid in the sorting operations. Push and pop functions are processed by the processing element to facilitate the loading of multiple data operands in the processing element.

Abstract: An ASCII-based processing system is disclosed. A memory is divided into a plurality of logical partitions. Each partition has a range of memory addresses and includes information associated with a particular task. Task information includes contents of task state register and one or more task data registers, with each task data register having an ASCII name. Each task data register is successively labeled with a unique alphabetic character label starting with the character ‘A.’ A dataflow unit within the processing system is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task. Task instructions can include ASCII characters that indicate a request for resources and indicate the ASCII-character designated names of task data registers on which the task instruction operates. A processing element receiving the task instruction performs the operation indicated by the ASCII operator code on the indicated task data registers.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller. The memory is organized into a set of logical partitions. Task partitions describe a task and include task state information, task data registers and ASCII task instructions. The task state information includes a set of index registers that are accessible by the task instructions. The index registers typically have dedicated locations in the task partition and are referred to by lower case ASCII alphabetic characters. Index registers are used to refer to a task partition in some cases or to a location in the current task partition in other cases for purposes of branching. Index registers can be incremented or decremented and loaded with an immediate data value. In one embodiment, the data flow unit is used to interpret the branch code and fetch contents of a named index register used in the branch.