Patents by Inventor Edwin M. Thurnau

Edwin M. Thurnau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6978386
    Abstract: A method for reducing thermal dissipation in a single PLC package includes implementing a pulse width modulated current regulator including a field effect transistor (FET) switch, and utilizing a turn on delay of the FET to provide a wide operating range of current. The FET has an inherent turn-on time delay that can be exploited such that, as the duty cycle is reduced, the FET's drain to source impedance dominates an inductive path of an output filter and increases output filtering.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: December 20, 2005
    Assignee: GE Fanuc Automation North America, Inc.
    Inventors: Ronald E. Gareis, Donald A. Gates, Edwin M. Thurnau
  • Patent number: 6816919
    Abstract: A control circuit for configuring at least one I/O module connector pin is provided. The circuit includes at least one port controlling a configuration of the at least one pin.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: November 9, 2004
    Assignee: GE Fanuc Automation North America, Inc.
    Inventors: Ronald E. Gareis, Edwin M. Thurnau, Derald Herinckx
  • Publication number: 20030014573
    Abstract: A control circuit for configuring at least one I/O module connector pin is provided. The circuit includes at least one port controlling a configuration of the at least one pin.
    Type: Application
    Filed: July 16, 2001
    Publication date: January 16, 2003
    Inventors: Ronald E. Gareis, Edwin M. Thurnau, Derald Herinckx
  • Publication number: 20020087895
    Abstract: A method for reducing thermal dissipation in a single PLC package includes implementing a pulse width modulated current regulator including a field effect transistor (FET) switch, and utilizing a turn on delay of the FET to provide a wide operating range of current. The FET has an inherent turn-on time delay that can be exploited such that, as the duty cycle is reduced, the FET's drain to source impedance dominates an inductive path of an output filter and increases output filtering.
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventors: Ronald E. Gareis, Donald A. Gates, Edwin M. Thurnau
  • Patent number: 5844430
    Abstract: An apparatus and method for controlling a variable threshold signal conditioning circuit to condition a variable amplitude periodic input signal in response to the control signals received. A plurality of transistor circuits, each responsive to a control signal, are disposed in parallel with the positive feedback resistor of a trigger circuit. The transistor circuits are controlled to adjust the upper threshold levels of the trigger circuit in order to reduce the false triggering effects of noise in the input signal. The lower threshold level is held constant at the input signal mid-line voltage while the upper threshold level is varied over a plurality of preprogrammed values. A microprocessor determines the appropriate threshold level for the circuit by comparing the timing signal output of the signal conditioning circuit to preprogrammed values stored in the microprocessor memory.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: December 1, 1998
    Assignee: Cummins Engine Company, Inc.
    Inventors: Edwin M. Thurnau, Ernest A. Streicher, Daniel D. Wilhelm