Patents by Inventor Edwin O'Yang

Edwin O'Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency
    Patent number: 7512729
    Abstract: A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: Bijoy Bose, Sridhar Lakshmanamurthy, Mark B. Rosenbluth, Irwin J. Vaz, Suri Medapati, Edwin O'Yang
  • Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency
    Publication number: 20060221980
    Abstract: A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Bijoy Bose, Sridhar Lakshmanamurthy, Mark Rosenbluth, Irwin Vaz, Suri Medapati, Edwin O'Yang