Abstract: An integrated cable-ready digital TV receiver includes a digital TV receiver system, a cable receiver system, a power control system for controlling a first power supply to the digital TV receiver system and a second power supply to the cable receiver system. The power control system is configured to control the first and second power supply according to a condition including a first condition and a second condition of the integrated cable-ready digital TV. In the first condition, the power control system supplies the first power to the digital TV receiver system but does not provide the second power to the cable receiver system. In the second condition, the power control system supplies the first power to the digital TV receiver system and the second power to the cable receiver system.

Abstract: A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value.

Abstract: A variable length decoder for decoding a variable length code. The variable length decoder includes a first look-up table for receiving and decoding the most significant bits of the variable length code and for producing a first decoded code corresponding to the most significant bits. The first look-up table means also for outputs a conversion signal. In addition, a second look-up table is provided for receiving and decoding the least significant bits and for producing a second decoded code corresponding to the least significant bits. The first look-up table and the second look-up table decode the most significant bits and the least significant bits at substantially the same time. The decoded output of the look-up tables is provided to a selector. The selector selects the first decoded code or the second decoded code based upon the conversion signal.

Abstract: A method of splicing two compressed video signals which have been encoded according to the standard adopted by the Moving Picture Experts Group (MPEG) determines an amount of null information that is to be inserted between the two video signals in order to ensure that an input buffer of an MPEG decoder does not overflow after receiving the spliced video signals. The method allows a splice to occur after any access unit (picture) in the first compressed video signal. The amount of null information is determined from the data rates of the first and second compressed video signals and the amount of new data which is provided to the buffer before the data is retrieved from the buffer for both the first and second video signals. The video signals are spliced by inserting the null information, as sequence stuffing bits into a buffer immediately after the selected picture in the first video signal. The second video signal is transmitted to the buffer immediately after these stuffing bits.

Abstract: The present invention is embodied in a decoder for a video signal encoded according to the standard proposed by the Moving Pictures Expert Group (MPEG) of the International Standards Organization (ISO). This decoder employs four sets of processors, each set containing three processors that operate concurrently to decode the MPEG-2 video signal. A variable length decoder processes the input stream to decode the variable length encoded data. The operations performed by this decoding processor change depending on the type of data being decoded. These changes are implemented using a master Digital Signal Processor (DSP) which is programmed according to the MPEG-2 syntax. The data decoded by the VLD processor is either video data or control data. The control data is divided into two types, control data needed to reproduce the image and control data that describes the bit-stream.

Abstract: A system and method for filtering a digital signal having a relatively high data rate uses circuitry which operates at a lower data rate. The filter includes an input section which receives the input signal and which divides the input signal into a plurality of contiguous segments. The system also includes a first filter which receives samples representing one of the plurality of segments and adjacent samples from the next contiguous one of the segments and which filters all of the received samples to produce a first filtered signal. A second filter receives samples of the next contiguous segment and filters those samples to produce a second filtered signal. The filtered signals are combined by providing the samples of the second filtered signal immediately after the samples of the first filtered signal to produce a filtered output signal.

Abstract: Apparatus for selecting a block of data in a previous frame to be used as a predicted block for a given block in a current frame in a system that reduces the bit rate by codifying the difference between the predicted block and the given block in a given manner by deriving the differences between the given block in the current frame and a plurality of blocks in the previous frame and selecting as the predicted block that block for which the codification of its differences with the given block requires the least number of bits. The apparatus can also select a predicted block from a number of blocks selected in accordance with ABD or SBD techniques.

Abstract: A method and apparatus for synchronizing a received television signal to a subcarrier locked signal is provided. The apparatus includes a comparison block for determining whether the received television signal and subcarrier locked signal are related by a predetermined fixed frequency relationship and for providing indications of the same, and a signal generation block for dividing down the subcarrier locked signal according to the predetermined fixed frequency relationship so as to provide an output signal which is synchronized with the subcarrier locked signal, and at a frequency determined according to the fixed frequency relationship when the signals are related. The apparatus is particularly useful in PIP applications where the received television signal is a horizontal signal and the subcarrier locked signal is a four times multiple of the subcarrier frequency.

Abstract: Apparatus and methods for remodulating digital luminance and color difference components for display as PIP information, or together with other composite video components for multi-PIP and test pattern applications are disclosed. A digital encoder is used for conducting a digital quadrature modulation on the color difference components and for digitally adding the luminance signal thereto prior to the converting of the remodulated information into an analog format. Preferably, the digital video information output by the encoder is in the form Y1+(R-Y)1, Y1 +(B-Y)1, Y2-(R-Y)1, Y2-(B-Y)1, Y3+(R-Y)2. Y3+(b-Y)2, Y4 -(R-Y)2, . . . , where Y is the luminance component, R-Y and B-Y are color difference components, and where the numbers index received samples of the video components with the luminance component being sampled at twice the frequency of the color difference components.

Abstract: A stabilized gated oscillator that provides pulses at a predetermined repetition rate in phase coherence with a gating signal includes a ceramic resonator in a feedback resonant circuit between the output terminal and the input terminal of a linear amplifier. The resonant circuit, which establishes the repetition rate, is constructed to provide an oscillator frequency in a frequency range between two resonant frequencies of the ceramic resonator wherein the ceramic resonator acts as an inductance.

Abstract: A digital television processing section capable of picture enhancement, progressive scanning, and multiple picture-in-picture processing is provided. The preferred digital television processing section preferably comprises a picture enhancement processor (PEP), a progressive scan processor, a picture in picture processor, at least one multiplexing means, and a common memory means. The PEP broadly comprises a parameter control means, a memory input select means, and mixer for obtaining current video data, delayed video data from the common memory, and control information from the control means, and for processing the obtained data and information to provide a signal to the progressive scan processor. In various modes of operation, the mixer also provides the signal to the memory input select means which forwards the information to the common memory. The common memory is used as a field delay device and feeds a delayed signal forward to the progressive scan processor.