Abstract: A data storage device with a cache memory in communication with a control processor programmed with a routine to effect data throughput with a host device. The data storage device includes a head-disc assembly responsive to the control processor retrieving a host data along with a speculative data in a form of a read data. The control processor adjusting a range for acquisition of the speculative data based on data stored in cache memory fragments of the cache memory. The cache memory storing the read data in an unused cache memory fragment, while the control processor updates a history queue and a band count table based on the acquired read data and releases an oldest cache memory fragment with a lowest count value in the band count table from the cache memory in response to a need for cache memory space.

Abstract: Method and apparatus for transferring data between a host device and a data storage device having a first memory space (such as a buffer) and a second memory space (such as magnetic discs). Data are stored on the discs in host-addressable data sectors. The data storage device is configured to operate in a local mode of operation and a nonlocal mode of operation. During the local mode, nonrequested user data are retrieved from the discs and placed into the buffer in anticipation of a future request for the nonrequested user data. During nonlocal mode, such nonrequested user data are not retrieved. An interface circuit monitors host data access patterns and dynamically switches between the nonlocal and local modes in relation to proximity of a data sector address of each most recently received read command to data sector addresses associated with previously received read commands.

Abstract: Method and apparatus for transferring data between a host device and a data storage device having a first memory space and a second memory space. The host issues access commands to store and retrieve data. The device stores commands in the first memory space pending transfer to the second memory space. An interface circuit evaluates relative proximity of first and second sets of LBAs associated with pending first and second commands, and delays promotion of later pending commands in front of earlier pending commands during an overlap condition. If the overlap is caused by performance enhancing features (PEF) the PEFs are disabled so the commands can be scheduled for disc access. Indicators are set in the commands to signal that a PEF has caused the overlap and that PEF can be disabled. Values are added to indicators in the commands such that the PEFs can be modified and avoid overlaps.

Abstract: Method and apparatus for transferring data between a host device and a data storage device having a first memory space and a second memory space. The host issues access commands to store and retrieve data. The device stores write data associated with write commands in the first memory space pending transfer to the second memory space. An interface circuit evaluates relative proximity of first and second sets of LBAs associated with pending first and second write commands, and forms an adaptive bidirectional write skip mask when the sets of LBAs fit within a predetermined mask interval. The mask is preferably slidably adjustable to encompass both sets of LBAs and is preferably expandable to accommodate additional sets of LBAs. The data within the mask are treated as a combined write command and are thereafter written in an order corresponding to an order in which the data appear in the mask.

Abstract: A system for evaluating whether an interface between a host device and a target device complies with specifications of an industry standard, such as, without limitation, SCSI, Serial ATA, Parallel ATA and Fibre Channel Arbitrated Loop, is disclosed. The system scans a communication trace between the host device and the target device to detect a timing measure present in the communication trace. The timing measure begins with a start condition and terminates with an ending condition. The start and ending conditions may be functions of logic transitions on either multiple or single signal lines in the communication trace. After a timing measure is detected, the system evaluates the length of the timing measure against a timing measure protocol specified by the industry standard. A computer-readable program storage device which tangibly embodies a program of instructions executable by a computer system for evaluating whether the interface complies with the industry standard is also disclosed.