Abstract: A resistive sensor includes a current input sigma-delta converter that uses a switched offset voltage source to provide scalable gain and more linear operation. The sigma-delta converter includes an integrator, a quantizer, and a decimator. In one embodiment, the resistive sensor and offset voltage source are coupled to provide an input current at a first node. The integrator has a first input terminal coupled to the first node, and an output terminal. The quantizer has a first input terminal coupled to the output terminal of the integrator, a second input terminal for receiving a clock signal, and an output terminal coupled to provide a feedback signal to control the offset voltage source. The decimator has an input terminal coupled to the output terminal of the quantizer, and an output terminal for providing an output signal. The switched offset voltage source provides scalable gain and good linearity.

Abstract: A sensor system is disclosed. The sensor system includes a first sensor path comprising a first sensing element and a second sensing element being connected in series between a first supply terminal and a second supply terminal and an intermediate node connected in between the first supply terminal and the second supply terminal, a second sensor path comprising a third sensing element and a fourth sensing element connected in series between the first supply terminal and the second supply terminal, a first reference node connected in between the first supply terminal and the second supply terminal, and a second reference node connected in between the first supply terminal and the second supply terminal, and a processing unit to receive an input signal from the intermediate node, a first reference signal from the first reference node, and a second reference signal from the second reference node.

Abstract: Systems and methods for providing an output signal based at least in part upon an input signal and a clock signal in a manner in which jitter is avoided or diminished, including for example a digital-to-analog converter (DAC), are disclosed herein. In one example embodiment, such a system includes an output signal generating component, a first component having a first switch and a variable characteristic, and a plurality of second components each having a respective additional switch and a respective fixed characteristic. A value of the variable characteristic is set at least in part based upon input and clock signals so that, when the variable characteristic influences at least indirectly the generating of the output signal by the output signal generating component, the output signal attains a first level that at least indirectly depends upon a phase of the clock signal relative to the input signal.

Abstract: A sensor circuit incorporates an analog to digital converter for providing a digital signal derived from sensing elements connected in a bridge configuration. The sensor circuit comprises first and second paths comprising respective first and second sensing elements connected between first and second supply lines; an analog to digital converter having a differential input connected to receive a differential voltage signal (Vinp?Vinn) between the first and second sensing elements and an output for providing a digital output signal (Dout) representing a difference between the first and second sensing elements, the analog to digital converter comprising: current sources connected between the first and second supply lines, each current source being switchably connected to either the first or second sensing elements; and control logic configured to selectively switch current from each of the current sources to either the first path or the second path in dependence on the differential voltage signal.

Abstract: A sensor circuit incorporates an analogue to digital converter for providing a digital signal derived from sensing elements connected in a bridge configuration. The sensor circuit comprises first and second paths comprising respective first and second sensing elements connected between first and second supply lines; an analogue to digital converter having a differential input connected to receive a differential voltage signal (Vinp-Vinn) between the first and second sensing elements and an output for providing a digital output signal (Dout) representing a difference between the first and second sensing elements, the analogue to digital converter comprising: current sources connected between the first and second supply lines, each current source being switchably connected to either the first or second sensing elements; and control logic configured to selectively switch current from each of the current sources to either the first path or the second path in dependence on the differential voltage signal.

Abstract: It is described a sensor system (100, 200, 300) comprising (a) a first sensor path (110) comprising a first sensing element (111) and a second sensing element (112) being connected in series between a first supply terminal (st1) and a second supply terminal (st2) and an intermediate node (in, in1) being provided in between the first supply terminal (st1) and the second supply terminal (st2), (b) a second sensor path (120) comprising (b1) a third sensing element (123) and a fourth sensing element (124) being connected in series between the first supply terminal (st1) and the second supply terminal (st2), wherein the third sensing element (123) is subdivided into a first third subcomponent (R3a) and a second third subcomponent (R3b) and the fourth sensing element (124) is subdivided into a first fourth subcomponent (R4a) and a second fourth subcomponent (R4b), (b2) a first reference node (rn1) being provided in between the first supply terminal (st1) and the second supply terminal (st2), and (b3) a second refer

Abstract: In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream.

Abstract: In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream.

Abstract: In a signal processor, a sampling arrangement (SH11, S12, SH13, ADC1) samples at least a first signal (YA) and a second signal (UA, VA) so as to obtain sampled first signal (YD1) and a sampled second signal (UD1, VD1), respectively. A folding compensator (LPF11, LPF12, LPF13, SUB11, SUB12, MUX12) compensates for a folding component in the sampled first signal (YD1) on the basis of a spectral portion of the sampled second signal (UD1, VD1) that is substantially free of components that originate from the second signal (UA, VA).

Abstract: From a television signal data such as teletext or closed caption data is extracted by slicing. A binary data signal is formed dependent on whether the television signal level is above or below a slicing level (S). The slicing level (S) is selected by defining a reconstructed data signal (D) with signal values equal to plus and minus an amplitude value relative to a middle level and transitions between these signal values at time points where the television signal crosses the slicing level. An auxiliary signal (R) is formed that contains the television signal (Vi) from which the reconstructed data signal (D) has been subtracted. A feedback loop is provided that adapts the amplitude value (A) to regulate a residual data signal amplitude in the auxiliary signal (R) to zero.

Abstract: Circuit arrangement, LIN comprising such circuit arrangement as well as method for processing input signals of the LIN In order to further develop a circuit arrangement (100)—for processing at least one input signal (12) from at least one data bus (10) of at least one LIN and—for providing the data bus (10) with at least one output signal (18), as well as a corresponding operating method in such way that EMI performance and/or EMI performance of the LIN (300) is improved, it is proposed to provide—at least one analog-digital converting circuit (ADC) for converting the analog input signal (12) into at least one digital signal (14) to be processed, and—at least one digital-analog converting circuit (DAC) for converting the processed digital signal (16) into the analog output signal (18).

Abstract: Circuit arrangement, L[ocal]I[nterconnected]N[etwork] comprising such circuit arrangement as well as method for processing input signals of the LIN In order to further develop a circuit arrangement (100)—for processing at least one input signal (12) from at least one data bus (10) of at least one L[ocal]I[nterconnected]N[etwork] and—for providing the data bus (10) with at least one output signal (18), as well as a corresponding operating method in such way that E[lectro]M[agnetic]E[mission] performance and/or E[lectro]M[agnetic]I[mmunity] performance of the L[ocal]I[nterconnected]N[etwork] (300) is improved, it is proposed to provide—at least one analog-digital converting means (ADC) for converting the analog input signal (12) into at least one digital signal (14) to be processed, and—at least one digital-analog converting means (DAC) for converting the processed digital signal (16) into the analog output signal (18).

Abstract: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40?) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50?) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40?)

Abstract: In a signal processor, a sampling arrangement (SH11, S12, SH13, ADC1) samples at least a first signal (YA) and a second signal (UA, VA) so as to obtain sampled first signal (YD1) and a sampled second signal (UD1, VD1), respectively. A folding compensator (LPF11, LPF12, LPF13, SUB11, SUB12, MUX12) compensates for a folding component in the sampled first signal (YD1) on the basis of a spectral portion of the sampled second signal (UD1, VD1) that is substantially free of components that originate from the second signal (UA, VA).

Abstract: A processor reduces periodic interference signal components in an input signal to obtain a desired signal. The desired signal has a predefined characteristic during an interval of time. First, an interference-representing signal (S1-S13) is stored (SWM1, C1-C13) on the basis of the input signal that occurs within the interval of time during which the desired signal has the predefined characteristic. The interference-representing signal (S1-S13) represents at least one period of a periodic interfering signal. Then, on the basis of the interference-representing signal (S1-S 13), compensation (ICS) is repetitively provided (SWM2, SUB) for the periodic interfering signal.

Abstract: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40?) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50?) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40?)

Abstract: From a television signal data such as teletext or closed caption data is extracted by slicing. A binary data signal is formed dependent on whether the television signal level is above or below a slicing level (S). The slicing level (S) is selected by defining a reconstructed data signal (D) with signal values equal to plus and minus an amplitude value relative to a middle level and transitions between these signal values at time points where the television signal crosses the slicing level. An auxiliary signal (R) is formed that contains the television signal (Vi) from which the reconstructed data signal (D) has been subtracted. A feedback loop (34, 36, 37, 38, 32) is provided that adapts the amplitude value (A) to regulate a residual data signal amplitude in the auxiliary signal (R) to zero. The slicing level (S) is determined from a difference between television signal (Vi) and from a television signal data such as teletext or closed caption data is extracted by slicing.