Abstract: Method and apparatus for skew error measurement and correction in a digital-to-analog converter (DAC) using a time-to-digital converter (TDC). A DAC includes a main DAC and a TDC. The main DAC includes a plurality of DAC cells. The main DAC is configured to generate an analog output signal based on digital input data. The TDC is coupled to an output of the main DAC and configured to measure a timing error of the main DAC. The timing error may be measured on a DAC cell basis or a subset of DAC cells basis.

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

Abstract: A multi-device system and a method for phase alignment of multiple devices in a multi-device system. The system includes a plurality of devices, a plurality of clock dividers, and a delay circuit. The plurality of devices are configured to operate based on a first clock signal. The clock dividers are configured to generate a second clock signal from the first clock signal and provide the second clock signal to the devices. The delay circuit is configured to incur a specific delay to the second clock signal provided to the devices such that a phase of the second clock signal provided to the devices is spread over time. Each of the clock dividers may be reset based on a reference clock signal provided to each clock divider, and the delay circuit may incur the specific delay on the reference clock signal provided to each clock divider.

Abstract: A system and method for testing or determining a phase noise and/or jitter of a phase locked loop (PLL). The system includes a first PLL configured to generate a first clock signal based on a reference clock signal, a first buffer for providing the reference clock signal to the first PLL, a mixer configured to mix the first clock signal with a second clock signal, an analog-to-digital converter (ADC) configured to convert an output of the mixer to digital data, and a processing circuit configured to process the digital data to determine a phase noise or jitter of the first PLL and generate an output indicative of the phase noise or jitter of the first PLL. The system may include a second PLL configured to generate the second clock signal based on the reference clock signal, and a second buffer for providing the reference clock signal to the second PLL.

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

Abstract: A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

Abstract: A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.

Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.

Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.

Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.

Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.

Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.

Abstract: One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies.

Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.