Patents by Inventor Edwin Thaller
Edwin Thaller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230236999Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.Type: ApplicationFiled: December 26, 2020Publication date: July 27, 2023Inventors: Kameran Azadet, Wee Liew, Ramani Tatikola, Edwin Thaller, Patrick Torta, Yu-Shan Wang, Georg Weber, James Yoder
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Patent number: 11489538Abstract: A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.Type: GrantFiled: September 28, 2018Date of Patent: November 1, 2022Assignee: Intel CorporationInventors: Edwin Thaller, Christian Lindholm
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Publication number: 20210218410Abstract: A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.Type: ApplicationFiled: September 28, 2018Publication date: July 15, 2021Inventors: Edwin Thaller, Christian Lindholm
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Patent number: 10651869Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.Type: GrantFiled: March 26, 2019Date of Patent: May 12, 2020Assignees: Intel IP Corporation, Intel CorporationInventors: Davide Ponton, Michael Kalcher, Alan Paussa, Edwin Thaller, Franz Kuttner, Daniel Gruber
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Patent number: 9571108Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.Type: GrantFiled: November 17, 2014Date of Patent: February 14, 2017Assignee: Infineon Technologies AGInventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
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Patent number: 9083362Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.Type: GrantFiled: July 8, 2011Date of Patent: July 14, 2015Assignee: INFINEON TECHNOLOGIES AGInventors: Davide Ponton, Edwin Thaller, Nicola Da Dalt
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Publication number: 20150070060Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.Type: ApplicationFiled: November 17, 2014Publication date: March 12, 2015Inventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
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Patent number: 8891679Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.Type: GrantFiled: January 3, 2014Date of Patent: November 18, 2014Assignee: Infineon Technologies AGInventors: Stefano Marsili, Giuseppe Li Puma, Stefan Van Waasen, Yanzhong Dai, Edwin Thaller
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Patent number: 8890592Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.Type: GrantFiled: October 13, 2012Date of Patent: November 18, 2014Assignee: Infineon Technologies AGInventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
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Patent number: 8779867Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.Type: GrantFiled: October 26, 2011Date of Patent: July 15, 2014Assignee: Intel Mobile Communications GmbHInventors: Edwin Thaller, Roberto Nonis
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Publication number: 20140119476Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.Type: ApplicationFiled: January 3, 2014Publication date: May 1, 2014Applicant: Infineon Technologies AGInventors: Stefano Marsili, Giuseppe Li Puma, Stefan Van Waasen, Yanzhong Dai, Edwin Thaller
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Publication number: 20140103976Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.Type: ApplicationFiled: October 13, 2012Publication date: April 17, 2014Inventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
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Patent number: 8625708Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.Type: GrantFiled: September 8, 2010Date of Patent: January 7, 2014Assignee: Infineon Technologies AGInventors: Stefano Marsili, Giuseppe Li Puma, Stefan Van Waasen, Yanzhong Dai, Edwin Thaller
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Publication number: 20130107978Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicant: Intel Mobile Communications GmbHInventors: Edwin Thaller, Roberto Nonis
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Patent number: 8373472Abstract: One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies.Type: GrantFiled: June 20, 2011Date of Patent: February 12, 2013Assignee: Intel Mobile Communications GmbHInventors: Edwin Thaller, Stefano Marsili, Giuseppe Li Puma
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Publication number: 20130009473Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.Type: ApplicationFiled: July 8, 2011Publication date: January 10, 2013Inventors: Davide PONTON, Edwin THALLER, Nicola DA DALT
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Publication number: 20120319749Abstract: One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies.Type: ApplicationFiled: June 20, 2011Publication date: December 20, 2012Applicant: Intel Mobile Communications GmbHInventors: Edwin Thaller, Stefano Marsili, Giuseppe Li Puma
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Patent number: 8248157Abstract: Implementations of differential variable capacitance systems are disclosed.Type: GrantFiled: February 25, 2009Date of Patent: August 21, 2012Assignee: Infineon Technologies AGInventor: Edwin Thaller
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Publication number: 20120057655Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.Type: ApplicationFiled: September 8, 2010Publication date: March 8, 2012Applicant: Infineon Technologies AGInventors: Stefano Marsili, Giuseppe Li Puma, Stefan Van Waasen, Yanzhong Dai, Edwin Thaller
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Publication number: 20120049907Abstract: In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.Type: ApplicationFiled: November 4, 2011Publication date: March 1, 2012Applicant: Infineon Technologies AGInventors: Nicola Da Dalt, Edwin Thaller