Patents by Inventor Edzel Gerald Dela Cruz Raffinan

Edzel Gerald Dela Cruz Raffinan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-test solution for delay locked loops
    Patent number: 9977077
    Abstract: A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: May 22, 2018
    Assignee: Bitmicro LLC
    Inventor: Edzel Gerald Dela Cruz Raffiñan
  • Self-test solution for delay locked loops
    Patent number: 9423457
    Abstract: A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 23, 2016
    Assignee: BiTMICRO Networks, Inc.
    Inventor: Edzel Gerald Dela Cruz Raffiñan
  • Self-Test Solution For Delay Locked Loops
    Publication number: 20140285211
    Abstract: A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 25, 2014
    Inventor: Edzel Gerald Dela Cruz Raffinan