Abstract: A digital-to-analog converter includes an adder having a plurality of inputs and an output coupled to the output of the converter. The converter further includes a plurality of digital-to-analog (DAC) elements, each DAC element has an output coupled to an input of the adder, and each DAC element has a DAC element input. A plurality of comparators have outputs coupled to a DAC element input. A first input of each comparator is coupled to the input of the converter. A second input of each comparator is selectively coupled to one of a predetermined voltage and a pseudo-random bit sequence (PRBS[n]).

Abstract: This disclosure includes an analog-to-digital converter (ADC) including multiple digital-to-analog converter (DAC) elements and multiple comparators, with an output of each of the comparators provided to an input of a different one of the multiple DAC elements. The ADC also includes a first voltage connection provided to each of the multiple comparators and multiple second voltage connections, with a different second voltage connection provided to each of the multiple comparators. The ADC further includes first and second resistor ladders, with the first resistor ladder configured to be switchably coupled to a first voltage supply and the second resistor ladder configured to be switchably coupled to a second voltage supply. Each of the second voltage connections is configured to be switchably coupled to a different one of the nodes in the first resistor ladder and to a different one of the nodes in the second resistor ladder.

Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

Abstract: A current digital-to-analog converter (DAC) and an integrated circuit chip including the DAC are disclosed. The current DAC includes a switching circuit that includes a plurality of switches coupled to receive differential digital control signals and to provide first and second differential current outputs, a current source coupled to an upper rail and to a first node of the switching circuit, a first current sink coupled to a lower rail and to a second node of the switching circuit, and an interference cancellation circuit coupled to substantially prevent a tail capacitance current from flowing through the first and second differential current outputs.

Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

Abstract: The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

Abstract: The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

Abstract: A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog input signal and an output of a digital to analog converter. A comparator receives an output of the loop filter and generates a digital output signal. A reference select logic unit receives the digital output signal as a feedback and generates one or more switching signals. One or more switches are coupled to the comparator and each switch receives a pre-computed reference voltage. The one or more switches are activated by the one or more switching signals in response to the digital output signal.

Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.

Abstract: A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog input signal and an output of a digital to analog converter. A comparator receives an output of the loop filter and generates a digital output signal. A reference select logic unit receives the digital output signal as a feedback and generates one or more switching signals. One or more switches are coupled to the comparator and each switch receives a pre-computed reference voltage. The one or more switches are activated by the one or more switching signals in response to the digital output signal.

Abstract: DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed.

Abstract: DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed.