Abstract: An aggregate die comprises a substrate, a first sub die, and a second sub die. The substrate comprises a surface with a first set of substrate alignment guides and a second set of substrate alignment guides. The first sub die comprises a first set of sub die alignment guides that interface with the substrate alignment guides in the first set of substrate alignment guides. The second sub die comprises a second set of sub die alignment guides that interface with substrate alignment guides in the second set of substrate alignment guides.

Abstract: An approach for validating a logic key in an IC (integrated circuit) is disclosed. One approach includes an IC comprising of key input circuit couple to a fuse check circuit; charge pump circuit coupled to the fuse check circuit and a switch matrix; and one or more antifuse circuit connected to the switch matrix. Another approach comprises of a method including, inputting a secret key by a user; determining status of one or more antifuse circuit; validating the secret key; in responsive to the secret key not matching an original secret key, determining whether antifuse threshold has been reached; in responsive to determining that the antifuse threshold has been reached, disabling the IC; in responsive to the secret key matching the original secret key, enabling the IC; and in responsive to determining that the antifuse threshold has not been reached, activating the antifuse circuit.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, first and second field effect transistors (FETs) of opposite polarity, the first FET being disposed on a first side of the substrate and including first work function metal (WFM) and the second FET being disposed on a second side of the substrate and including second WFM, a first gate dielectric disposed over at least the first side of the substrate and a second gate dielectric disconnected from the first gate dielectric and disposed over at least the second side of the substrate. The second WFM is aligned with the second gate dielectric and the first WFM extends beyond the first gate dielectric.

Abstract: A semiconductor device comprises a stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel structures. Respective ones of the plurality of channel structures comprise a plurality of stacked semiconductor layers. At least two of the plurality of stacked semiconductor layers in the respective ones of the plurality of channel structures comprise different materials from each other.

Abstract: A semiconductor structure includes a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include a first gate with nanosheet layers of high-K metal gate (HKMG) and gate channel, a second gate with nanosheet layers of HKMG and gate channel, a source/drain (S/D) channel having a single continuous material between the first gate and the second gate, and inner spacers between the HKMG and the S/D channel.

Abstract: A semiconductor structure includes a plurality of gate-all-around field effect transistors, each of the gate-all-around field effect transistors including: first and second source-drain regions; a plurality of nanowire channels interconnecting the first and second source-drain regions; and a common gate. The common gate includes an upper gate portion above the plurality of nanowire channels and a lower gate portion surrounding the plurality of nanowire channels. A unitary spacer structure includes an upper spacer portion between the upper gate portion and the first and second source-drain regions and a lower spacer portion between the lower gate portion and first and second source-drain regions. The upper spacer portion and the lower spacer portion have aligned left and right edges.

Abstract: A security key associated with a plurality of programmable switches included in an integrated circuit is received. The plurality of programmable switches are set causing the plurality of programmable switches to be conductive. Reset pulses are applied to a first set of programmable switches included in the plurality of programmable switches based on the received security key.

Abstract: A redistribution layer for an integrated circuit package is provided. The redistribution layer includes a first conductive layer and a second layer disposed directly on the first conductive layer. The first conductive layer has a resistivity of less than 3.6*10?8 ?·m and has a thickness of greater than or equal to 1 ?m. The second layer includes tungsten. An integrated circuit package is also provided that includes the redistribution layer electrically connecting a first integrated circuit of the first integrated circuit package to a first input/output of a frame of the integrated circuit package. The frame is connected to the first integrated circuit. A method for manufacturing a redistribution layer is also provided.

Abstract: 3D NOR flash memory devices having vertically stacked memory cells are provided. In one aspect, a memory device includes: a word line/bit line stack with alternating word lines and bit lines separated by dielectric layers disposed on a substrate; a channel that extends vertically through the word line/bit line stack; and a floating gate stack surrounding the channel, wherein the floating gate stack is present between the word lines and the channel, and wherein the bit lines are in direct contact with both the channel and the floating gate stack. Techniques for configuring the memory device for neuromorphic computing are provided, as are methods of fabricating the memory device.

Abstract: Aspects of the subject disclosure may include, for example, a method in which a processing system receives an alert for delivery to user equipment devices (UEs) communicating on a network. The system determines a type of the alert and a coverage area for the alert; identifies UEs in the coverage area for delivery of the alert; and determines, for each of the UEs, a priority level for the alert, and selects, for each of the UEs, a delivery profile for delivering the alert; the delivery profile is based on the type of the alert and comprises the priority level, and specifies a manner of presenting the alert at the UE, based on the priority level. The system then delivers the alert to each of the plurality of target UEs respectively in accordance with the delivery profile. Other embodiments are disclosed.

Abstract: A semiconductor structure comprises a semiconductor substrate including a first silicon substrate component having a first crystalline orientation and a second silicon substrate component over the first silicon substrate and having a second crystalline orientation different from the first crystalline orientation. The semiconductor substrate defines a trench extending through the second silicon substrate component and at least partially within the first silicon substrate component. A gallium nitride structure is disposed within the trench of the semiconductor substrate.

Abstract: Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.

Abstract: A stacked field effect transistor device is provided. The stacked field effect transistor device includes a lower semiconductor channel segment between a first pair of source/drains, and an upper semiconductor channel segment between a second pair of source/drains. The stacked device further includes a gate dielectric layer on the upper and lower semiconductor channel segments, and a first work function material layer on the gate dielectric layer on the lower semiconductor channel segment. The stacked device further includes a first conductive gate fill on the first work function material layer, and a replacement work function material layer on the gate dielectric layer on the upper semiconductor channel segment and the first conductive gate fill, wherein the replacement work function material layer is a different work function material from the first work function material layer. The device further includes a replacement conductive gate fill on the replacement work function material layer.

Abstract: The technologies described herein are generally directed to using dynamically layered beamformed control signals in a fifth generation (5G) network or other next generation networks. For example, a method described herein can include, identifying a group of different directions radiating from beamforming antenna equipment of base station equipment. The method can further include facilitating transmitting a first beamformed signal according to a first direction of the group of different directions. Further, the method can include facilitating transmitting a second beamformed signal according to a second direction of the group of different directions, with the second direction being selected based on a sequence of directions, and where transmitting beamformed signals to the group of different directions is based on the sequence of directions can facilitate establishment of wireless coverage for a corresponding geographic area.

Abstract: The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

Abstract: Systems and methods for attaching a virtual input device to a virtual object in a mixed reality (MR) environment are provided. The system includes a memory, a processor communicatively coupled to the memory, and a display device. The display device is configured to display a MR environment provided by at least one application implemented by the processor. The mixed reality environment includes a virtual object corresponding to an application, and a virtual input device. The at least one application docks the virtual input device to the virtual object with an offset relative to the virtual object.

Abstract: The disclosure is directed to apparatus and methods for manufacturing including a collaborative robot, a camera operatively coupled to the collaborative robot, a memory coupled to the collaborative robot, and processing circuitry coupled to the memory, the processing circuitry configured to receive image data of at least one component intended for a printed circuit board (PCB), the image data collected by the camera operatively coupled to the collaborative robot, determine, based on the image data, a coordinate location for the component, and secure the component to the PCB using an end effector of the collaborative robot based on the received image data. In one embodiment, the collaborative robot is configured to operate alongside a human, the collaborative robot in combination with the camera configured to manufacture a computer system with the PCB.

Abstract: An electrolytic capacitor can be located in a notch in a side of a PCB with its pins resting on electrical contact pads on the surface of the PCB in a pair of channels in the upper side of the PCB extending away from the sides of the cavity and attached to the contact pads by solder paste. Alternately, the contact pads are on the upper surface of the PCB and the capacitor is located in the cavity with its pins bending upward and then back to be parallel with the upper PCB to attach to the contact pads. The pins and contact pads can be on the same side of the capacitor and cavity or on opposite sides. For smaller devices, such as a ceramic capacitors, a cavity is set into the surface of the PCB and the capacitor's terminals connected to contact pads by wire bounding.

Abstract: The technologies described herein are generally directed to using dynamically layered beamformed control signals in a fifth generation (5G) network or other next generation networks. For example, a method described herein can include, identifying a group of different directions radiating from beamforming antenna equipment of base station equipment. The method can further include facilitating transmitting a first beamformed signal according to a first direction of the group of different directions. Further, the method can include facilitating transmitting a second beamformed signal according to a second direction of the group of different directions, with the second direction being selected based on a sequence of directions, and where transmitting beamformed signals to the group of different directions is based on the sequence of directions can facilitate establishment of wireless coverage for a corresponding geographic area.

Abstract: Semiconductor devices having gate all around transistors with dual channels, one channel type for p-channel field-effect transistors (pFETs) and another channel type for n-channel field-effect transistors (nFETs) are provided. In one aspect, a semiconductor device includes: a wafer; and at least a first transistor and a second transistor on the wafer, where the first and second transistors each includes multiple channels, and where the multiple channels of the first transistor include first portions and second portions with the first portions having (e.g., Si) cores and a (e.g., SiGe) ciadding layer fully surrounding the cores. Alternatively, an anneal can be performed to convert the cores/cladding layer into uniform (e.g., SiGe). A method of fabricating the present semiconductor devices is also provided.