Abstract: An ultranarrow insulated trench isolation structure is formed in a semiconductor substrate without creating voids in the insulating material which adversely affect the performance of finished devices. Embodiments include forming a narrow trench in the semiconductor substrate, then forming a spacer on the sidewalls of the trench, as by depositing and anisotropically etching a layer of silicon dioxide, amorphous silicon, or silicon oxynitride. The trench is then refilled as by conventional LPCVD, PECVD or HDP techniques, and the spacers are oxidized, if necessary. Since the spacers, in effect, create sloped trench walls, the trench fill can be performed, even at a high deposition rate, with substantially fewer voids than conventional processes, while also reducing reentrance of the trench walls.

Abstract: The present invention is an improved semiconductor device and an improved method of manufacturing a semiconductor device. The present invention deposits a layer of oxynitride where gate oxidation would normally take place. Alternatively, the method according to the present invention uses a plurality of layers of dielectric material where gate oxidation would normally take place including a layer of oxynitride having a nitrogen content. The layer of oxynitride is deposited under a predetermined pressure using a stream of gas, wherein insensitivity to defects on a surface of the substrate results from the oxynitride layer.

Abstract: This invention provides methods for manufacturing anti-reflective barrier and/or polish-stop layers on semiconductors. The anti-reflective barrier and/or polish-stop layers permit more accurate photolithography during the manufacture of semiconductor devices. The barrier and/or polish-stop layers can comprise nitride and/or oxynitride films having non-stoichiometric ratios of silicon to nitrogen atoms within the film structure. The non-stoichiometry permits the films to be semi-transparent, decreasing transmission of electromagnetic radiation through the layers, thereby decreasing the reflection of the electromagnetic radiation back through the photoresist layers. By decreasing the reflection of the electromagnetic radiation through the photoresist materials, the effects of diffraction by mask edges and standing wave interference can be reduced, thereby permitting the more accurate, reproducible inscription of patterns onto semiconductor devices.

Abstract: Dual gate oxide layer thicknesses are achieved by depositing a thin blocking layer on active regions of a semiconductor substrate, such as silicon nitride, oxynitride, or oxide. Selected active regions are nitridated through a patterned photoresist mask formed thereon. The blocking layer protects the substrate from the photoresist mask and enables nitriding, as by ion implantation, plasma exposure, or rapid thermal annealing.

Abstract: Methodology for achieving dual field oxide thicknesses comprises forming field oxide isolation regions to a common thickness. An oxidation barrier layer, which may comprise nitride or oxynitride, is formed on selected field oxide regions leaving others exposed. The exposed field oxide regions are enlarged in a complementary thermal oxidation step, wherein the isolation regions covered by the oxidation barrier layer are not enlarged, thereby achieving field oxide regions of at least two thicknesses.

Abstract: A shallow trench isolation structure having rounded corners is formed at edge-rounding oxidation temperatures employing a two-step trench etching technique. Isotropic etching is first performed, undercutting a pad oxide layer and a barrier nitride layer. Subsequently, anisotropic etching is conducted to form the remainder of the trench. The isotropic etch enables the thermal oxidation to form an oxide liner with rounded edges and reduced stress at relatively low temperatures, e.g. 900° C. or less, even using water vapor as the oxidizing species.

Abstract: Dual gate oxide layer thicknesses are achieved by depositing a thin blocking layer on active regions of a semiconductor substrate, such as silicon nitride, oxynitride, or oxide. Selected active regions are nitridated through a patterned photoresist mask formed thereon. The blocking layer protects the substrate from the photoresist mask and enables nitriding, as by ion implantation, plasma exposure, or rapid thermal annealing.

Abstract: A shallow trench isolation structure is formed with a nitridated oxide liner on the sides and edges of the trench, thereby reducing interfacial strain. Embodiments include forming a trench opening in a monocrystalline silicon substrate or in an epitaxial layer formed thereon. An oxide liner is formed at the internal surface of the trench opening in a nitrous oxide ambience, creating flexible silicon-nitrogen (Si--N) bonds which relieves stress induced at the side walls and edges of the trench. The lined trench opening is then filled with an insulating material.

Abstract: The present invention provides an improved semiconductor device and method of impeding the diffusion of boron by providing at least one layer of polysilicon and an interface substance. A semiconductor device according to the present invention is comprised of a substrate; gate oxide coupled to the substrate; a layer of polysilicon coupled to the gate oxide; and an interface layer between the layer of polysilicon and the gate oxide, wherein the interface layer impedes diffusion of doping material.

Abstract: A method of manufacturing a semiconductor device to negate the effects on the device performance caused by defects on the silicon substrate. An oxygen doped amorphous silicon layer is deposited onto the gate region of the semiconductor device and can have a thickness of less than 5 nanometers. The amorphous silicon provides a conformal layer over the defects on the silicon substrate. The oxygen doping of the amorphous silicon maintains the conformality of the amorphous silicon layer during subsequent processing by preventing the formation of large amorphous silicon grains during a crystallization process. The resulting silicon oxide layer has increased uniformity and can have a thickness of less than 10 nanometers.

Abstract: A method of manufacturing a semiconductor device to prevent uneven polysilicon gate dopant accumulation at the gate/gate oxide interface. A layer of gate oxide is formed on the surface of the silicon substrate, a layer of amorphous silicon is deposited on the gate oxide and a doped layer of amorphous silicon is deposited on the first layer. The first and second layers are deposited by chemical vapor deposition and an oxygen containing gas is selectively injected into the stream of silicon source gas depositing the first and second layers of amorphous silicon.

Abstract: A semiconductor fabrication technique is provided for producing a low resistivity polycide. Polycide resistivity is lowered by minimizing areas where the polycide is unduly thin. By preparing the polysilicon upper surface prior to polycide formation thereon, the polysilicon surface can grow polycide at a uniform rate across the entire polysilicon surface. The polysilicon surface is prepared by either restricting doping atoms at grain boundary locations at the polysilicon surface, or by disrupting the grain boundaries by ion implanting that surface. In either instance, a properly prepared polysilicon surface greatly enhances the conductivity of polycide grown thereon.

Abstract: An improved process is provided for forming a highly planar BPSG interlevel dielectric. The process includes using a silane based source material placed within a plasma enhanced CVD chamber. The plasma enhanced CVD chamber undergoes high energy plasma deposition by applying an RF energy exceeding 950 watts in order to minimize formation of silicon-rich intermediates upon the semiconductor substrate. Moreover, densification of the BPSG material occurs within an oxygen ambient to enhance the formation of silicon dioxide having a flow angle substantially less than lower power, non-oxygen densified processes. Still further, BPSG can, if desired, be selectively etched to form a more planarized topography or a possibly recessed topography. Selective etching is brought about by a photolithography mask used to form the underlying conductors.

Abstract: A method of field isolation of a semiconductor circuit includes forming a silicon oxide layer over the surface of a substrate, depositing a layer of silicon nitride overlying said silicon oxide layer, patterning said silicon oxide and silicon nitride layers to provide openings and exposing portions of said substrate, forming trench regions in said openings, forming a spin-on-glass (SOG) layer over said silicon nitride layer and in said trench regions, curing and annealing at a first temperature the SOG layer after it is formed, oxidizing the SOG layer at a second temperature, wherein the second temperature is less than first temperature, and patterning the oxidized SOG layer to expose the oxidized SOG layer formed in the trench regions.

Abstract: The invention provides a method for manufacturing a non-volatile, virtual ground memory element. The method includes the steps of depositing a first polysilicon layer on gate oxide on a silicon substrate, depositing or growing a first oxide layer, depositing a barrier nitride layer and patterning the first polysilicon layer, the first oxide layer and the barrier nitride layer to form a floating gate. The method further includes the steps of doping a region of the silicon substrate adjacent the floating gate to form a bit line region and oxidizing the bit line region in a wet ambient. The method further includes the use of a spacer nitride or spacer oxide/nitride layer to protect the edge of the floating gate during oxidation and to reduce dopant diffusion under the gate. The method further includes the steps of stripping the barrier nitride layer, depositing a second polysilicon layer and patterning the second polysilicon layer to form a control gate.

Abstract: A method of fabricating a high-quality tunnel oxide layer includes a two-step oxidation process. The first oxidation step includes oxidizing a substrate in an atmosphere comprising oxygen and nitrogen at a temperature of approximately 950.degree. C., and thus is an HCl-less oxidation. The second oxidation step is performed in an atmosphere comprising HCl and argon at a temperature of approximately 1050.degree. C. The first oxidation step is performed at a temperature in the range of temperatures for the viscous flow of the oxide to prevent any physical defects from forming in the oxide layer. The second oxidation step is performed at a temperature sufficient to passivate any mobile ions in the oxide layer in at atmosphere comprising a gettering agent, for example, HCl. By this two-step oxidation process a tunnel oxide layer which is of high quality and is not damaged during subsequent processing steps performed at temperatures at 1100.degree. C. and above.