Abstract: In one embodiment, a process for fabricating a high-K layer comprising the steps of: placing a semiconductor substrate into a first chamber of a deposition apparatus; supplying high-K precursors to the deposition apparatus; generating ions or molecules of high-K material from the high-K precursors in a second chamber of the deposition apparatus, the second chamber being remote from the first chamber; passing the ions or molecules of high-K material from the second chamber to the first chamber; and depositing a high-K layer upon the semiconductor substrate.

Abstract: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a stacked polysilicon layer formed on a dielectric layer. The stacked polysilicon layer inhibits the diffusion of boron in the dielectric layer and the penetration of boron into the dielectric layer and the semiconductor substrate.

Abstract: A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region between an opposing source lateral region and a drain lateral region. A control gate is positioned above the multilevel charge trapping dielectric. The multilevel charge trapping dielectric comprises a tunnel dielectric layer adjacent the substrate, a top dielectric adjacent the control gate, and a charge trapping dielectric positioned there between. The thickness of the tunnel dielectric layer in the central region is greater than a thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.

Abstract: A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof; and a layer of a high-K dielectric material. The device may further include a second interfacial barrier layer on the high-K dielectric material layer, and may further include a polysilicon or polysilicon-germanium gate electrode formed on the second interfacial barrier layer.

Abstract: In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.

Abstract: An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.

Abstract: A method for making an SOI semiconductor device including a silicon substrate includes implanting oxide and Nitrogen into the substrate and then annealing to drive Oxygen and Nitrogen through and below the buried oxide layer. The implanted species interact with the Silicon matrix of the substrate to establish field isolation areas that extend deeper than the buried oxide layer of the SOI device, to ensure adequate component isolation.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: An apparatus and method used in extracting polysilicon gate doping from C−V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.

Abstract: A process for fabricating a semiconductor device, including providing a semiconductor substrate; depositing on the semiconductor substrate a layer of a high-K gate dielectric material; depositing on the gate dielectric material layer a polysilicon or polysilicon-germanium gate electrode layer, in which the step of depositing the polysilicon or polysilicon-germanium gate electrode layer includes providing non-reducing conditions in a CVD apparatus.

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Oxide base film on a substrate, and then annealing the substrate in ammonia. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract: This invention discloses a method of editing, accessing, creating, and retrieving database information in a medical services business wirelessly. The wireless device could be a PDA, laptop, a computer, or any telephony device. The database information extends from pre-admission, to treatment, to post-admission, hospitalization, and post-hospitalization data. It also covers EMS operations and interactions with hospitals. It covers patient and physician history and laboratory diagnosis. It describe method of wirelessly generating healthcare provider notes and the authentication of such notes. The information transmittal is secured by an elaborate authenticating scheme disclosed here. The disclosure covers all fields and activities of current medical care now transformed from wired or paper to wireless by various devices.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its deposition, e.g., by ion implantation, to augment its etch rate with a room temperature etchant, e.g., dilute aqueous HF. The treated spacers are removed with the dilute, aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract: Methods of manufacturing insulating materials having high dielectric constants are disclosed, in which the high-dielectric constant material is deposited on a semiconductor surface that has been treated to remove layers of low-dielectric constant dielectric material which form on the surfaces of semiconductor wafers during manufacturing and conventional wafer preparation. During conventional wafer preparation, a layer of oxide forms on the surface of the semiconductor substrate. The oxide has a lower dielectric constant than the desired high-dielectric constant insulator, therefore, the presence of this layer of native oxide effectively lowers the dielectric constant of the overall insulating film. The methods of this invention involve heating the wafer in an environment containing an oxide reducing material. The oxide reducing material chemically reduces the semiconductor substrate, thereby decreasing the amount of oxide present on the surface of the wafer.

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Nitrogen Oxide base film on a substrate, and then annealing the substrate in ammonia. An ultra-thin nitride film is deposited on the base film. The semiconductor device is then oxidized in Nitrogen Oxide. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches.

Abstract: Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for “latch up” are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate insulator layer.

Abstract: Sub-micron-dimensioned, asymmetrically-configured MOS and/or CMOS transistors are fabricated using removable sidewall spacers made of a material, such as UV-nitride, one of which is selectively treated subsequent to deposition, e.g., by ion implantation, to augment the etch rate thereof with a room temperature etchant, e.g., dilute aqueous HF. The treated spacer is removed with the dilute, aqueous HF prior to implantation of asymmetrically-configured, moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of heavily-sloped source/drain junction regions but prior to annealing of the implant for dopant diffusion/activation and lattice damage relaxation. Lightly-or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: In order to form a self-aligned damascene gate which enables the resistance of the gate to be reduced, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annealed. The dielectric layer is polished for planarity using a chemical-mechanical-polishing (CMP) technique or the like. A gate mask is then used to pattern the dielectric, the interlayer dielectric (ILD) is etched, and the resist is stripped. A gate dielectric is deposited in the form of a CVD nitride, oxynitride, or stacked nitride oxide ONO, or the like. Polysilicon is then deposited over the dielectric, doped by implantation, and annealed. A silicon rich silicide layer is then deposited after which CMP or the like is used to remove the superfluous portions of the silicide, doped polysilicon and gate oxide layers down to the dielectric level.