Abstract: A secure processing engine and method configured to protect a computing system are provided. The system includes a first processor configured to provide real-time protection to at least processes executed over the main processor of the protected computing system; and a direct memory access (DMA) configured to provide an access to a main memory of the main processor, wherein the first processor is coupled to the DMA and further configured to monitor the at least processes by accessing the main memory via the DMA; wherein the first processor operates in an execution environment in complete isolation from an execution environment of the main processor.

Abstract: A secure processing engine and method configured to protect a computing system are provided. The system includes a first processor configured to provide real-time protection to at least processes executed over the main processor of the protected computing system; and a direct memory access (DMA) configured to provide an access to a main memory of the main processor, wherein the first processor is coupled to the DMA and further configured to monitor the at least processes by accessing the main memory via the DMA; wherein the first processor operates in an execution environment in complete isolation from an execution environment of the main processor.

Abstract: A method, and processor for securing a host platform of a computing device are presented. The method includes generating, by a security processor, a first graph based on at least a portion of executable code, wherein the executable code is executed by a main processor of the host platform; generating a metadata file based on the generated first graph; polymorphing the executable code based on the generated metadata file; generating a second graph based on the polymorphed code; creating slices of the polymorphed code; executing at least one slices of the created slices by the security processor, wherein the security processor is apart from the main processor; polymorphing the at least one of executed slice; and pairing the least polymorphed slice with the polymorphed code.

Abstract: A sanitization circuit for sanitizing and authenticating a semiconductor device and method thereof are provided. The sanitization circuit is integrated in the semiconductor device and includes a memory verification module configured to verify any pre-programmed memory integrated in the semiconductor device; a memory eraser module configured to erase data stored in at least volatile memory accessed by the semiconductor device; and an implanted circuitry detection module configured to detect any unintended circuitry added to the semiconductor device.

Abstract: A method, and processor for securing a host platform of a computing device are presented. The method includes generating, by a security processor, a first graph based on at least a portion of executable code, wherein the executable code is executed by a main processor of the host platform; generating a metadata file based on the generated first graph; polymorphing the executable code based on the generated metadata file; generating a second graph based on the polymorphed code; creating slices of the polymorphed code; executing at least one slices of the created slices by the security processor, wherein the security processor is apart from the main processor; polymorphing the at least one of executed slice; and pairing the least polymorphed slice with the polymorphed code.

Abstract: An attack resilient distributed proactive polymorphic hardware, the including: at least one polymorphic core including at least one polymorphic logic, the at least one polymorphic logic adapted to adjust an implementation of a proactive polymorphic model without changing the contextual functionality of the proactive polymorphic model; a framework list defining at least one policy to be executed by the proactive polymorphic model; and a graph designating a historical description of each of the at least one policy executed by the proactive polymorphic model.

Abstract: A method, and processor for securing a host platform of a computing device are presented. The method includes generating, by a security processor, a first graph based on at least a portion of executable code, wherein the executable code is executed by a main processor of the host platform; generating a metadata file based on the generated first graph; polymorphing the executable code based on the generated metadata file; generating a second graph based on the polymorphed code; creating slices of the polymorphed code; executing at least one slices of the created slices by the security processor, wherein the security processor is apart from the main processor; polymorphing the at least one of executed slice; and pairing the least polymorphed slice with the polymorphed code.

Abstract: A system and method for the generation of a trusted polymorphic and distributed unique hardware identifier (ID) are provided. The method includes checking a device for a current ID; selecting a polymorphic policy setting randomly when no current ID is detected, wherein the polymorphic policy setting defines a functionality of at least one function of the device; selecting functional steps of the at least one function randomly, wherein the functional steps are selected from a number of states of a finite-state machine (FSM) used to construct the at least one function; pairing an output DNA mechanism to the at least one function; and generating the unique ID based on the paired DNA mechanism, its structure and its functional operation.

Abstract: An anti-tampering protection assembly for sensing tampering with at least one conductor, the anti-tampering protection assembly including unpredictably varying signal generating circuitry, connected to the at least one conductor, for providing unpredictably varying signals on the at least conductor and tampering sensing circuitry for sensing tampering with the at least one conductor.

Abstract: An anti-tampering protection assembly for sensing tampering with at least one conductor, the anti-tampering protection assembly including unpredictably varying signal generating circuitry, connected to the at least one conductor, for providing unpredictably varying signals on the at least conductor and tampering sensing circuitry for sensing tampering with the at least one conductor.

Abstract: An anti-tampering protection assembly for sensing tampering with at least one conductor, the anti-tampering protection assembly including unpredictably varying signal generating circuitry, connected to the at least one conductor, for providing unpredictably varying signals on the at least conductor and tampering sensing circuitry for sensing tampering with the at least one conductor.

Abstract: An anti-tampering protection assembly for sensing tampering with at least one conductor, the anti-tampering protection assembly including unpredictably varying signal generating circuitry, connected to the at least one conductor, for providing unpredictably varying signals on the at least conductor and tampering sensing circuitry for sensing tampering with the at least one conductor.