Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.

Abstract: An electrically erasable/programmable CMOS logic memory cell for RFID applications and other mobile applications includes a tunneling capacitor, a control capacitor, and a CMOS inverter that share a single floating gate. A two-phase program/erase operation performs an initial Fowler-Nordheim (F-N) injection phase using the capacitors, and then a Band-to-Band Tunneling (BBT) phase using the CMOS inverter. Both the F-N injection and BBT phases are performed using low currents and low voltages (i.e., 5V or less). The tunneling and control capacitors are fabricated in isolated P-wells (IPWs) including both N+ and a P+ regions to enable the use of both positive and negative programming voltages during the F-N and BBT programming/erasing operations.

Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.

Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.

Abstract: An electrically erasable/programmable CMOS logic memory cell for RFID applications and other mobile applications includes a tunneling capacitor, a control capacitor, and a CMOS inverter that share a single floating gate. A two-phase program/erase operation performs an initial Fowler-Nordheim (F-N) injection phase using the capacitors, and then a Band-to-Band Tunneling (BBT) phase using the CMOS inverter. Both the F-N injection and BBT phases are performed using low currents and low voltages (i.e., 5V or less). The tunneling and control capacitors are fabricated in isolated P-wells (IPWs) including both N+ and a P+ regions to enable the use of both positive and negative programming voltages during the F-N and BBT programming/erasing operations.

Abstract: A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.

Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.

Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.

Abstract: A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.

Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.

Abstract: A self-aligned process for fabricating a non-volatile memory cell having two isolated floating gates. The process includes forming a gate dielectric layer over a semiconductor substrate. A floating gate layer is then formed over the gate dielectric layer. A disposable layer is formed over the floating gate layer, and patterned to form a disposable mask having a minimum line width. Sidewall spacers are formed adjacent to the disposable mask, and source/drain regions are implanted in the substrate, using the disposable mask and the sidewall spacers as an implant mask. The disposable mask is then removed, and the floating gate layer is etched through the sidewall spacers, thereby forming a pair of floating gate regions. The sidewall spacers are removed, and an oxidation step is performed, thereby forming an oxide region that surrounds the floating gate regions. A control gate is then formed over the oxide region.

Abstract: A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.

Abstract: A self-aligned process for fabricating a non-volatile memory cell having two isolated floating gates. The process includes forming a gate dielectric layer over a semiconductor substrate. A floating gate layer is then formed over the gate dielectric layer. A disposable layer is formed over the floating gate layer, and patterned to form a disposable mask having a minimum line width. Sidewall spacers are formed adjacent to the disposable mask, and source/drain regions are implanted in the substrate, using the disposable mask and the sidewall spacers as an implant mask. The disposable mask is then removed, and the floating gate layer is etched through the sidewall spacers, thereby forming a pair of floating gate regions. The sidewall spacers are removed, and an oxidation step is performed, thereby forming an oxide region that surrounds the floating gate regions. A control gate is then formed over the oxide region.

Abstract: A method for etching an oxide-nitride-oxide (ONO) layer fabricated on a semiconductor wafer, the ONO layer including a lower oxide layer, a nitride layer located over the lower oxide layer, and an upper oxide layer located over the nitride layer. The method includes the steps of removing the upper oxide layer and a portion of the nitride layer using an isotropic plasma enhanced etch, and then removing the remainder of the nitride layer and a portion of the lower oxide layer using an isotropic plasma enhanced etch, wherein the semiconductor wafer is not exposed through the lower oxide layer. The method can be used to form gate electrodes and diffusion bit liens in a fieldless array of non-volatile memory cells.

Abstract: A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.

Abstract: A semiconductor process is provided that creates fully-salicided transistors. in a first region and partially-salicided transistors in a second region. Each of the fully-salicided transistors includes a salicided gate electrode and salicided active regions. Each of the partially-salicided transistors includes a salicided gate electrode and active regions that are free from salicide. A silicide blocking layer prevents the formation of salicide in the active regions of the partially-salicided transistors. The silicide blocking layer is deposited over the first and second regions, and then removed over the first region. The remaining portion of the silicide blocking layer over the second region is then etched back until the upper surfaces of the gate electrodes in the second region are exposed. The remaining portions of the silicide blocking layer covers the active regions in the second region. A refractory metal is then deposited over the resulting structure and reacted.

Abstract: A fieldless array of floating gate transistors is fabricated by forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate. A mask is formed over the ONO layer, the mask having openings that define a plurality of bit line regions of the floating gate transistors in the substrate. A first impurity is implanted into the bit line regions of the substrate, wherein the first impurity is implanted through the ONO layer, through the openings of the mask. The first impurity is implanted at various angles, such that the first impurity is implanted in the substrate at locations beneath the mask. The upper oxide and nitride layers of the ONO layer are subsequently etched through the mask openings. A second impurity is implanted in the substrate through the openings of the mask. The mask is removed, and the substrate is oxidized, thereby forming bit line oxide regions over the bit line regions, and floating gate structures.

Abstract: A method for etching an oxide-nitride-oxide (ONO) layer fabricated on a semiconductor wafer, the ONO layer including a lower oxide layer, a nitride layer located over the lower oxide layer, and an upper oxide layer located over the nitride layer. The method includes the steps of removing the upper oxide layer and a portion of the nitride layer using an isotropic plasma enhanced etch, and then removing the remainder of the nitride layer and a portion of the lower oxide layer using an isotropic plasma enhanced etch, wherein the semiconductor wafer is not exposed through the lower oxide layer. The method can be used to form gate electrodes and diffusion bit liens in a fieldless array of non-volatile memory cells.