Abstract: A dynamic bus inversion (DBI) circuit disposed between a transmitter and a receiver for generating an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver includes a delay data setup circuit to receive the data from the transmitter. A majority vote function circuit is used to perform majority voting for consecutive bits of data output by the delay data setup circuit to generate majority data output. An inversion control circuit receives the majority data output, retrieves feedback data from a preceding inversion control output and interprets the two data to generate inversion control signal, which is used to perform inversion control on data along the data path before being communicated to the receiver. The inversion control signal is used by the receiver to interpret the data received from the data path.

Abstract: A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.

Abstract: A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.

Abstract: A dynamic bus inversion (DBI) circuit disposed between a transmitter and a receiver for generating an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver includes a delay data setup circuit to receive the data from the transmitter. A majority vote function circuit is used to perform majority voting for consecutive bits of data output by the delay data setup circuit to generate majority data output. An inversion control circuit receives the majority data output, retrieves feedback data from a preceding inversion control output and interprets the two data to generate inversion control signal, which is used to perform inversion control on data along the data path before being communicated to the receiver. The inversion control signal is used by the receiver to interpret the data received from the data path.

Abstract: Systems and related methods are described for (1) determining one or more state probabilities for one or more states in a trellis representation; (2) determining an estimate of or extrinsic output for a bit using a trellis representation; (3) performing a MAX* 2?>1 operation; and (4) computing forward state probabilities in a forward mode of operation and computing backward state probabilities in a backward mode of operation. Combinations of the foregoing are also described.

Abstract: Systems and related methods are described for (1) determining one or more state probabilities for one or more states in a trellis representation; (2) determining an estimate of or extrinsic output for one or more bits using a trellis representation; (3) determining a branch metric for a branch in a trellis representation; (4) performing a MAX*2->1 operation; (5) performing a MAX*2p->1 operation, where p is an integer of two or more, through a hierarchical arrangement of MAX*2->1 operations; and (6) computing forward state probabilities in a forward mode of operation and computing backward state probabilities in a backward mode of operation. Combinations of the foregoing are also described.

Abstract: Systems and related methods are described for (1) determining one or more state probabilities for one or more states in a trellis representation; (2) determining an estimate of or extrinsic output for one or more bits using a trellis representation; (3) determining a branch metric for a branch in a trellis representation; (4) performing a MAX*2->1 operation; (5) performing a MAX*2p->1 operation, where p is an integer of two or more, through a hierarchical arrangement of MAX*2->1 operations; and (6) computing forward state probabilities in a forward mode of operation and computing backward state probabilities in a backward mode of operation. Combinations of the foregoing are also described.