Patents by Inventor Egidius Gerardus Petrus van Doren

Egidius Gerardus Petrus van Doren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7490178
    Abstract: A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the total number of such context switches. The threshold mechanism is associated with a buffer into which the producer stores packets up to a given threshold before the consumer is allowed to remove packets. The buffer has an associated upper limit on the number of packets that can be stored in the buffer. A flush empties the buffer of any remaining packets when no more packets are to be produced. This reduction in the total number of context switches in general leads to better performance at the cost of more latency.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: February 10, 2009
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Egidius Gerardus Petrus van Doren, Hendrikus Christianus Wilhelmus van Heesch
  • Publication number: 20040255305
    Abstract: A pattern of very fine features (18) can be produced by illuminating an inorganic negative tone resist layer (16), provided on an electroplating base layer (14), by a beam (EB), which is able to cure the resist to a cured pattern according to the pattern to be formed, removing the non-illuminated portions of the resist layer and electroplating a layer (20) between the cured portions (18) of the resist layer.
    Type: Application
    Filed: April 20, 2004
    Publication date: December 16, 2004
    Inventors: Egidius Gerardus Petrus Van Doren, Hendrikus Christianus Wilhemus Van Heesch
  • Publication number: 20040193775
    Abstract: Method for dynamically allocating/de-allocating memory pools (0, 1, 2, 3) in a physical memory of a computer comprising the steps of: allocating a memory area (4) for said memory pools (0, 1, 2, 3) within said physical memory, allocating said at least one memory block (2a, 2b) within each of said at least one memory pool (0, 1, 2, 3), and writing data in said at least one memory block (2a). To enable dynamic memory allocation, and to reduce memory fragmentation it is proposed that said at least one memory block (2a) is de-allocated after said at least one memory block (2a) is marked empty, and that at least one memory block (2a) is re-allocated within said memory area (4), whereby said memory block (2a) is moved within said memory area (4) during said de-allocation/re-allocation of said at least one memory block (2a, 2b).
    Type: Application
    Filed: February 10, 2004
    Publication date: September 30, 2004
    Inventors: Egidius Gerardus Petrus Van Doren, Hendrikus Christianus Wilhelmus Van Heesch