Patents by Inventor Egil D. Castel

Egil D. Castel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4839311
    Abstract: An improved method for the etch-back planarization of interlevel dielectric layers provides for cessation of the etch-back upon exposure of an indicator layer. the indicator layer, usually a metal, metal nitride, or silicon nitride is formed either within the dielectric or over an underlying metallization layer prior to patterning by conventional photolithographic techniques. A sacrificial layer, typically an organic photoresist, is then formed over the dielectric layer. Because of the presence of both relatively narrow and relatively broad features in the metallization, the thickness of the sacrificial layer will vary over features having different widths. As etch back planarization proceeds, the indicator layer which is first encountered releases detectable species into the planarization reactor. Detection of these species indicates that removal of the overlying dielectric layers to a predetermined depth is achieved.
    Type: Grant
    Filed: November 21, 1988
    Date of Patent: June 13, 1989
    Assignee: National Semiconductor Corporation
    Inventors: Paul E. Riley, Vivek D. Kulkarni, Egil D. Castel
  • Patent number: 4824521
    Abstract: A method for forming vertical metal interconnects on a semiconductor substrate having an uneven surface comprises first forming a laminated metal structure over the entire substrate. The laminated metal structure includes a first metallization sublayer, an intermediate etch stop barrier layer, and a second metallization sublayer. Usually, a barrier layer will be formed between the substrate and the laminated metal structure. The laminated metal structure is then patterned into the desired vertical metal interconnects, which interconnects are at different elevations because of the uneven underlying surface. The vertical metal interconnects are then planarized by first applying a dielectric layer and a sacrificial layer, etching back the combined dielectric and sacrificial layers to expose only the higher vertical metal interconnects, and then selectively etching back the second metal sublayer component of the higher vertical metal interconnects.
    Type: Grant
    Filed: April 1, 1987
    Date of Patent: April 25, 1989
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Vivek D. Kulkarni, Egil D. Castel
  • Patent number: 4167805
    Abstract: An improved method for fabrication of a photovoltaic cell preferably of the CdS--Cu.sub.x S type, having a copper electrode adjacent the Cu.sub.x S. A portion of the CdS is converted to Cu.sub.x S through ion exchange wherein the CdS is immersed in a first solution of cuprous ions and a second solution of cupric ions to produce a non-stoichiometric Cu.sub.x S. A layer of metallic copper is applied by conventional techniques, such as vacuum deposition, and the photovoltaic cell heat treated to affect formation of the CdS--Cu.sub.x S heterojunction. Metallic copper diffusing through the CdS and Cu.sub.x S from the electrode is captured by the non-stoichiometric Cu.sub.x S whereby the Cu.sub.x S is substantially stoichiometric in the completed photovoltaic cell.
    Type: Grant
    Filed: July 17, 1978
    Date of Patent: September 18, 1979
    Assignee: Photon Power, Inc.
    Inventor: Egil D. Castel