Patents by Inventor Egino Sarto

Egino Sarto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8006216
    Abstract: Techniques are disclosed for performing topologically planar routing of System in Packages (SiPs). A routing graph can be represented by a particle-insertion-based constraint Delaunay triangulation (PCDT) and its dual. A dynamic search routing may be performed using a DS* routing algorithm to determine the shortest path on the dual graph between a start point and an end point. Based on a dynamic pushing technique, net ordering problems may be solved. A first wire can be topologically routed. Dynamic search routing of a second wire may be performed. The first wire may be pushed or detoured in response to the dynamic searching routing of a second wire.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 23, 2011
    Assignee: Magma Design Automation, Inc.
    Inventors: Guoqiang Chen, Kaushik Sheth, Egino Sarto, Shenghua Liu
  • Patent number: 6389581
    Abstract: An aspect of interconnect design for optimizing delay characteristics of interconnects. The interconnect design for delay characteristics optimization is performed using a method for optimizing repeaters positioning along interconnects. The method includes inserting repeaters in positions along a first interconnect at predetermined intervals that are related to signals transition time. The method further includes inserting repeaters in positions along a second interconnect at the predetermined intervals, the second interconnect being a neighbor of the first interconnect. The positions of repeaters along the second interconnect are offset, by a predetermined length, relative to the positions of repeaters along the first interconnect so that the repeaters positions along the second interconnect are shifted relative to the repeaters positions along the first interconnect. In one embodiment, the predetermined length is half (0.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: May 14, 2002
    Assignee: Silicone Graphics Inc.
    Inventors: Sudhakar Muddu, Egino Sarto
  • Patent number: 6353917
    Abstract: Determining a switching factor is useful for optimizing integrated circuit (IC) design. One aspect of the invention is a method for determining the switching factor. The method includes applying a voltage to each interconnect of a pair of interconnects, each voltage having a waveform and a slew time. The method includes dividing the voltage waveform into time regions, and analyzing a behavior of a capacitor in each of the time regions by determining the value of an effective capacitance as seen from one of the interconnects. The method includes determining a total effective capacitance by time averaging the effective capacitance values and determining the switching factor from the total effective capacitance. The switching factor is a function of a ratio between the slew times, wherein a time-averaged effective value of the switching factor corresponds total effective capacitance.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: March 5, 2002
    Assignee: Silicon Graphics, Inc.
    Inventors: Sudhakar Muddu, Egino Sarto