Abstract: In a logic circuit arrangement comprising a plurality of sticks formed by series arrangements of transistors which receive the signals to be processed a conductive stick not only has to discharge the output capacitance of the logic output but also other sticks which are not completely conductive, namely up to the first cut-off transistor. This may result in a very high capacitive load, which substantially reduces the maximum attainable switching speed. In accordance with the invention an additional transistor is arranged between each stick and the output of the entire logic circuit, which transistor receives a gate voltage such that current flow from the cut-off charged sticks via a conductive stick is prevented or delayed until the output signal of the logic circuit has assumed a value which unambiguously switches over the next output transistor.

Abstract: Some known logic MOS circuits operated too slowly because too many "branches" were connected to a node of the circuit to be charged or discharged for the information transfer. The invention relates to a circuit arrangement with isolated branches, so that a faster clock signal can be used, which results in faster operation of the circuit.