Patents by Inventor Egon Ronny PFÜTZNER

Egon Ronny PFÜTZNER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUITS WITH STRAINED SILICON AND METHODS FOR FABRICATING SUCH CIRCUITS
    Publication number: 20150076559
    Abstract: Integrated circuits with strained silicon and methods for fabricating such integrated circuits are provided. An integrated circuit includes a stack with a surface layer, an intermediate layer, and a base layer, where the surface layer overlies the intermediate layer, and the intermediate layer overlies the base layer. The surface layer and the base layer include strained silicon, where the silicon atoms are stretched beyond a normal crystalline silicon interatomic distance. The intermediate layer includes crystalline silicon germanium.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Kai Frohberg, Torsten Huisinga, Egon Ronny Pfuetzner
  • Integrated circuits including barrier polish stop layers and methods for the manufacture thereof
    Patent number: 8772154
    Abstract: Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 8, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Egon Ronny Pfützner, Carsten Peters, Jens Heinrich
  • INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF
    Publication number: 20120319285
    Abstract: Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Egon Ronny PFÜTZNER, Carsten PETERS, Jens HEINRICH