Patents by Inventor Egor A. Andreev

Egor A. Andreev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory that allows simultaneous read requests
    Patent number: 6886088
    Abstract: The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: April 26, 2005
    Assignee: LSI Logic Corporation
    Inventors: Egor A. Andreev, Anatoli A. Bolotov, Ranko Scepanovic, Alexander E. Andreev
  • Memory that allows simultaneous read requests
    Publication number: 20040107308
    Abstract: The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.
    Type: Application
    Filed: December 3, 2002
    Publication date: June 3, 2004
    Inventors: Egor A. Andreev, Anatoli A. Bolotov, Ranko Scepanovic, Alexander E. Andreev
  • Optimal clock timing schedule for an integrated circuit
    Patent number: 6615397
    Abstract: A netlist graph of an IC cell contains cell pin vertices, auxiliary vertices, and edges between vertices having a length. A clock shift SH(V) is assigned to each auxiliary vertex so that for any two auxiliary vertices, a difference between the clock shift of the two auxiliary vertices is no greater than a design time of the two auxiliary vertices. The clock shift is assigned such that SH(V1)+DELAY(V1,V2)−SH(V2)≦f·BOUND(V1,V2), where SH(V1) and SH(V2) are the clock shift of first and second auxiliary vertices, DELAY(V1,V2) is a maximal delay of the path between the first and second auxiliary vertices, f is a minimize constant, and BOUND(V1,V2) is a timing restriction of the first and second auxiliary vertices.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: September 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Alexander E. Andreev, Egor A. Andreev, Ivan Pavisic
  • Optimal clock timing schedule for an integrated circuit
    Publication number: 20020091983
    Abstract: A netlist graph of an IC cell contains cell pin vertices, auxiliary vertices, and edges between vertices having a length. A clock shift SH(V) is assigned to each auxiliary vertex so that for any two auxiliary vertices, a difference between the clock shift of the two auxiliary vertices is no greater than a design time of the two auxiliary vertices. The clock shift is assigned such that SH(V1)+DELAY(V1, V2)−SH(V2)≦f·BOUND(V1, V2), where SH(V1) and SH(V2) are the clock shift of first and second auxiliary vertices, DELAY(V1, V2) is a maximal delay of the path between the first and second auxiliary vertices, f is a minimize constant, and BOUND(V1, V2) is a timing restriction of the first and second auxiliary vertices.
    Type: Application
    Filed: January 8, 2001
    Publication date: July 11, 2002
    Inventors: Alexander E. Andreev, Egor A. Andreev, Ivan Pavisic