Patents by Inventor Ehrenfried Zschech

Ehrenfried Zschech has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metal line having an increased resistance to electromigration along an interface of a dielectric barrier layer by implanting material into the metal line
    Publication number: 20050046031
    Abstract: During the formation of a metallization layer of a semiconductor device, a cap layer is formed above a metal line and subsequently an implantation process is performed so as to modify the metal in the vicinity of the interface between the cap layer and the metal line. Consequently, an improved behavior in view of electromigration of the metal line may be obtained, thereby increasing device reliability.
    Type: Application
    Filed: March 30, 2004
    Publication date: March 3, 2005
    Inventors: Hans-Juergen Engelmann, Ehrenfried Zschech, Peter Huebler
  • Soft error resistant semiconductor device
    Publication number: 20040164409
    Abstract: A semiconductor device comprises a material layer adapted to efficiently stop alpha particles that are substantially generated within a solder bump of a flip chip device. The materials used for stopping the alpha particles are compatible with standard back-end processing and do not degrade adhesion of the solder bump to the remaining substrate. Moreover, a low electrical resistance is maintained and heat dissipation may be improved.
    Type: Application
    Filed: August 27, 2003
    Publication date: August 26, 2004
    Inventors: Gisela Schammler, Mathias Bottcher, Frank Kuechenmeister, Daniel Gehre, Ehrenfried Zschech
  • Method of sample preparation for electron microscopy
    Patent number: 6303399
    Abstract: A method is provided for preparing a sample for cross-section analysis by a transmission electron microscope. Semiconductor samples containing recessed portions or unfilled structures are filled with a filling material so as to produce a planar top surface onto which a metal layer can be deposited for thinning the sample to a thickness of less than 100 nm by an FIB technique.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: October 16, 2001
    Assignee: Advanced Micro Devices Inc.
    Inventors: Hans-Juergen Engelmann, Beate Volkmann, Ehrenfried Zschech