Patents by Inventor Ehsan Pakbaznia

Ehsan Pakbaznia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits
    Patent number: 7834684
    Abstract: In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: November 16, 2010
    Assignee: Fujitsu Limited
    Inventors: Farzan Fallah, Ehsan Pakbaznia, Massoud Pedram
  • Sizing and Placement of Charge Recycling (CR) Transistors in Multithreshold Complementary Metal-Oxide-Semiconductor (MTCMOS) Circuits
    Publication number: 20090174469
    Abstract: In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.
    Type: Application
    Filed: October 31, 2008
    Publication date: July 9, 2009
    Applicant: Fujitsu Limited
    Inventors: Farzan Fallah, Ehsan Pakbaznia, Massoud Pedram
  • Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) Circuits
    Publication number: 20090146734
    Abstract: In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to ground via a second sleep transistor, a second virtual ground node between the second circuit block and the second sleep transistor, and a transmission gate (TG) or a pass transistor connecting the first virtual ground node to the second virtual ground node to enable charge recycling between the first circuit block and the second circuit block during transitions by the first circuit block from active mode to sleep mode and the second circuit block from sleep mode to active mode or vice versa.
    Type: Application
    Filed: October 31, 2008
    Publication date: June 11, 2009
    Applicant: Fujitsu Limited
    Inventors: Farzan Fallah, Ehsan Pakbaznia, Massoud Pedram
  • Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits
    Patent number: 7400175
    Abstract: In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node between the second circuit block and the second sleep transistor. The circuit also includes a transmission gate (TG) or a pass transistor connecting the virtual ground node to the virtual supply node to enable charge recycling between the first circuit block and the second circuit block during transitions by the circuit between active mode and sleep mode.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: July 15, 2008
    Assignee: Fujitsu Limited
    Inventors: Farzan Fallah, Ehsan Pakbaznia, Massoud Pedram
  • Recycling Charge to Reduce Energy Consumption During Mode Transition in Muiltithreshold Complementary Metal-Oxide-Semiconductor (MTCMOS) Circuits
    Publication number: 20070279100
    Abstract: In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node between the second circuit block and the second sleep transistor. The circuit also includes a transmission gate (TG) or a pass transistor connecting the virtual ground node to the virtual supply node to enable charge recycling between the first circuit block and the second circuit block during transitions by the circuit between active mode and sleep mode.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 6, 2007
    Applicant: Fujitsu Limited
    Inventors: Farzan Fallah, Ehsan Pakbaznia, Massoud Pedram