Patents by Inventor Ehsan Rashid

Ehsan Rashid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for operating chips synchronously at speeds exceeding the bus speed
    Patent number: 5708801
    Abstract: A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: January 13, 1998
    Assignee: Hewlett-Packard Company
    Inventors: James B. Williams, Kenneth K. Chan, John F. Shelton, Ehsan Rashid
  • Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer
    Patent number: 5600824
    Abstract: A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: February 4, 1997
    Assignee: Hewlett-Packard Company
    Inventors: James B. Williams, Kenneth K. Chan, John F. Shelton, Ehsan Rashid